MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 9

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
0
14
M12, M11, M10 = “0, 0, 0”
BA1
to ensure compatibility
with future devices.
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
*Should program
13
BA0
0
12
A12
Reserved*
Mode Register Definition
11
A11
10
A10
WB
M9
0
1
9
A9
Op Mode
8
A8
7
A7 A6
Figure 1
Programmed Burst Length
M8
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
5
A5
M7
0
-
4
A4
M3
BT
Defined
M6-M0
0
1
3
A3
-
M6
M2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M1
M5
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
9
NOTE: 1. For full-page accesses: y = 512 (x16)
Length
Burst
Page
Full
(y)
2
4
8
2. For a burst length of two, A1-A8 (x16) select the
3. For a burst length of four, A2-A8 (x16) select the
4. For a burst length of eight, A3-A8 (x16) select the
5. For a full-page burst, the full row is selected and
6. Whenever a boundary of the block is reached
7. For a burst length of one, A0-A8 (x16) select the
Starting Column
block-of-two burst; A0 selects the starting column
within the block.
block-of-four burst; A0-A1 select the starting
column within the block.
block-of-eight burst; A0-A2 select the starting
column within the block.
A0-A8 (x16) select the starting column.
within a given sequence above, the following
access wraps within the block.
unique column to be accessed, and mode register
bit M3 is ignored.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A2 A1 A0
(location 0-y)
0
0
0
0
1
1
1
1
Address
n = A0-8
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 1
Type = Sequential Type = Interleaved
Cn, Cn + 1, Cn + 2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn + 3, Cn + 4...
Order of Accesses Within a Burst
MOBILE SDRAM
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x16
PRELIMINARY
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0