MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 28

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

CONCURRENT AUTO PRECHARGE
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs,
unless the SDRAM supports CONCURRENT AUTO
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
An access command (READ or WRITE) to another
precharge): A READ to bank m will interrupt a READ
Internal
States
NOTE: DQM is LOW.
READ With Auto Precharge Interrupted by a WRITE
Internal
States
NOTE: 1. DQM is HIGH at T2 to prevent D
READ With Auto Precharge Interrupted by a READ
COMMAND
ADDRESS
BANK m
BANK n
COMMAND
CLK
DQ
ADDRESS
BANK m
BANK n
DQM
CLK
DQ
1
Page Active
T0
NOP
Active
Page
READ - AP
BANK n,
BANK n
COL a
T0
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
Page Active
READ with Burst of 4
CAS Latency = 3 (BANK n)
T1
NOP
OUT
-a+1 from contending with D
Figure 25
Figure 24
T2
NOP
T2
NOP
28
BANK m,
READ - AP
T3
BANK m
COL d
T3
D
NOP
OUT
a
Interrupt Burst, Precharge
2. Interrupted by a WRITE (with or without auto
CAS Latency = 3 (BANK m)
READ with Burst of 4
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (Fig-
ure 25).
BANK m,
TRANSITIONING DATA
WRITE - AP
TRANSITIONING DATA
COL d
BANK m
T4
D
T4
d
IN
IN
Interrupt Burst, Precharge
NOP
-d at T4.
WRITE with Burst of 4
D
OUT
a
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RP - BANK n
T5
d + 1
NOP
D
T5
IN
NOP
t
RP - BANK n
D
a + 1
OUT
T6
d + 2
NOP
D
IN
T6
NOP
DON’T CARE
D
OUT
d
T7
t WR - BANK m
d + 3
NOP
D
MOBILE SDRAM
DON’T CARE
IN
Write-Back
Idle
Idle
T7
NOP
©2003 Micron Technology, Inc. All rights reserved.
t RP - BANK m
Precharge
D
d + 1
OUT
256Mb: x16
PRELIMINARY