MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 55

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
TIMING PARAMETERS
*CAS latency indicated in parentheses.
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
COMMAND
A0-A9, A11
AH
AS
CH
CL
CK (3)
CK (2)
CK (1)
CKH
CKS
BA0, BA1
DQM /
CKE
A10
CLK
DQ
2. PRECHARGE command not allowed else
3. x16: A9, A11 and A12 = “Don’t Care”
4. 14ns to 15ns is required between <D
t
WR has been increased to meet minimum
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
MIN
2.5
2.5
10
20
1
3
3
8
1
T1
NOP
SINGLE WRITE – WITHOUT AUTO PRECHARGE
-8
MAX
DISABLE AUTO PRECHARGE
t CMS
t CL
t DS
COLUMN m 3
WRITE
BANK
T2
D
MIN
2.5
2.5
10
12
25
IN
1
3
3
1
t CMH
t CH
t DH
m
t WR
-10
IN
MAX
4
m> and the PRECHARGE command, regardless of frequency. With a single write
t
RAS would be violated.
t
RAS requirement.
NOP 2
T3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
NOP 2
T4
SYMBOL*
t
t
t
t
t
t
t
t
t
CMH
CMS
DH
DS
RAS
RC
RCD
RP
WR
SINGLE BANK
PRECHARGE
ALL BANKS
T5
BANK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RP
T6
NOP
MIN
2.5
2.5
48
80
20
20
15
1
1
1
MOBILE SDRAM
-8
120,000
©2003 Micron Technology, Inc. All rights reserved.
MAX
ACTIVE
BANK
ROW
T7
256Mb: x16
PRELIMINARY
MIN
100
2.5
2.5
50
20
20
15
1
1
-10
120,000
NOP
MAX
T8
DON’T CARE
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns