MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 18

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

This is shown in Figure 7 for CAS latencies of two and
three; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. The 256Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
NOTE: Each READ command may be to either bank. DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
CAS Latency = 1
T0
T0
T0
BANK,
BANK,
BANK,
COL n
COL n
COL n
READ
READ
READ
CAS Latency = 2
Consecutive READ Bursts
CAS Latency = 3
T1
T1
T1
NOP
NOP
NOP
D
OUT
n
T2
T2
T2
NOP
NOP
NOP
Figure 7
D
D
n + 1
OUT
OUT
n
18
T3
T3
T3
NOP
NOP
NOP
D
n + 2
D
D
n + 1
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
OUT
OUT
OUT
n
TRANSITIONING DATA
T4
T4
T4
BANK,
BANK,
READ
BANK,
READ
COL b
READ
COL b
COL b
X = 0 cycles
X = 1 cycle
D
n + 3
D
n + 2
D
n + 1
OUT
OUT
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
n + 2
D
D
n + 3
OUT
OUT
OUT
b
T6
T6
NOP
NOP
D
n + 3
D
OUT
OUT
b
DON’T CARE
MOBILE SDRAM
T7
NOP
D
©2003 Micron Technology, Inc. All rights reserved.
OUT
b
256Mb: x16
PRELIMINARY