MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 12

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

sumed during refresh was unnecessarily high, because
the refresh rate was set to accommodate the higher
temperatures. Setting M4 and M3, allow the DRAM to
accomodate more specific temperature regions during
SELF REFRESH. There are four temperature settings,
which will vary the SELF REFRESH current according to
the selected temperature. This selectable refresh rate
will save power when the DRAM is operating at normal
temperatures.
PARTIAL ARRAY SELF REFRESH
the PASR feature allows the controller to select the
amount of memory that will be refreshed during SELF
REFRESH. The refresh options are four banks, two
banks (0 and 1), one bank (0), half bank (0 with internal
row address A12=0), and quarter bank (0 with internal
row address A12=0 and A11=0). WRITE and READ com-
mands can still occur during standard operation, but
only the selected banks will be refreshed during SELF
REFRESH. Data in banks that are disabled will be lost.
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
Thus, during ambiant temperatures, the power con-
For further power savings during SELF REFRESH,
12
DEEP POWER DOWN
maximum power reduction by eliminating the power
of the whole memory array of the devices. Data will not
be retained once the device enters Deep Power Down
Mode.
CS and /WE held low with /RAS and /CAS held high at
the rising edge of the clock, while CKE is low. This mode
is exited by asserting CKE high.
DRIVER STRENGTH
the DQ output drive strength. Full drive strength is
suitable for systems in which the SDRAM component
is placed on a module. Half drive strength is recom-
mended for point-to-point or other applications with
reduced output loading.
applications. Point-to-point systems are usually lightly
loaded with a memory controller accessing one to eight
SDRAM components on the memory bus with module
stubs between these devices. Driver strength chosen
should be load dependent. The lighter the load, the
less driver strength that is needed for the outputs.
This mode is entered by having all banks idle then /
Deep Power Down is an operating mode to achieve
Extended mode register bit A5 must be used to set
The half-strength can be used for point-to-point
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x16
PRELIMINARY