MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 21

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element n + 3 is either the last of a burst of
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
A fixed-length READ burst may be followed by, or
COMMAND
COMMAND
COMMAND
NOTE: DQM is LOW.
ADDRESS
ADDRESS
ADDRESS
CLK
CLK
CLK
DQ
DQ
DQ
CAS Latency = 1
BANK a,
BANK a,
BANK a,
COL n
COL n
COL n
T0
T0
T0
READ
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
T1
NOP
NOP
NOP
D
OUT
n
READ to PRECHARGE
T2
T2
T2
NOP
NOP
NOP
D
n + 1
D
OUT
OUT
n
Figure 11
T3
T3
T3
NOP
NOP
NOP
D
n + 2
D
D
n + 1
OUT
OUT
OUT
21
n
TRANSITIONING DATA
PRECHARGE
PRECHARGE
PRECHARGE
(a or all)
(a or all)
(a or all)
T4
BANK
T4
BANK
BANK
T4
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
that part of the row precharge time is hidden during
the access of the last data element(s).
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
X = 0 cycles
X = 1 cycle
D
n + 3
D
n + 2
D
n + 1
OUT
OUT
OUT
In the case of a fixed-length burst being executed to
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
n + 3
D
n + 2
OUT
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RP
t RP
t RP
T6
T6
T6
NOP
NOP
NOP
D
n + 3
OUT
DON’T CARE
BANK a,
BANK a,
BANK a,
ACTIVE
ACTIVE
ACTIVE
T7
T7
T7
ROW
ROW
ROW
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x16
PRELIMINARY
t
RP is met. Note