PNX1701EH,557 NXP Semiconductors, PNX1701EH,557 Datasheet - Page 797
PNX1701EH,557
Manufacturer Part Number
PNX1701EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1701EH557.pdf
(832 pages)
Specifications of PNX1701EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
3.5.1 Planar Variants
3.5 Planar YUV 4:2:0 and YUV 4:2:2 Formats
The spatial sampling structure of planar YUV 4:2:0 data is shown in
planar YUV 4:2:2 data has the spatial sampling structure as shown in
There are two variants of planar YUV 4:2:0 and YUV 4:2:2 formats.
Figure 6:
Figure 7:
Figure 8:
left-most pixel pair, 1st unit
memory address A
YUY2/2vuy Packed YUV 4:2:2 Format
Spatial Sampling Structure of Packed and Planar YUV 4:2:2 Data
Spatial Sampling Structure of YUV 4:2:0 Data
pair
Rev. 1 — 17 March 2006
1st unit
2nd unit
left-most pixel pair, 2nd unit
chrominance
samples
chrominance
samples
memory address A+2
15
31
luminance
samples
luminance
samples
V
U
. . . . . .
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 28: Pixel Formats
PNX17xx Series
8
24
right-most pixel pair, 2nd unit
7
23
memory address A+4k+2
16-bit word
Figure
1 byte
Figure
YUY2/2vuy
Y1
Y2
8. The
7.
28-6
0
16
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