PNX1701EH,557 NXP Semiconductors, PNX1701EH,557 Datasheet - Page 31
PNX1701EH,557
Manufacturer Part Number
PNX1701EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1701EH557.pdf
(832 pages)
Specifications of PNX1701EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 4: PNX1700 Interface
PNX17XX_SER_1
Preliminary data sheet
Pin Name
System Clock
XTAL_IN
XTAL_OUT
PCI_SYS_CLK
Miscellaneous System Interface
POR_IN_N
RESET_IN_N
SYS_RST_OUT_N
RESERVED
BGA
Ball
AB23 BPT3MCHDT5V
D11
E25
A11
D10
D9
C7
Remark: The pull-down in the BPT3MCHDT5V pads is NOT strong enough to
actually pull down a 5-V TTL input. Instead the TTL input pin sees a ‘1’.
Pad
Type
BPT3MCHT5V
BPT3MCHT5V
BPX2T14MCP
BPX2T14MCP
APIO1V2
APIO1V2
Rev. 1 — 17 March 2006
I/O
Type
OUT
OUT
OUT
I/O
IN
IN
IN
GPIO
#
-
-
-
-
-
-
-
P Description
U This clock is intended for use as the PCI clock in
U PNX1700 Power On Reset input. Asserting this
U PNX1700 reset input. Asserting this input low
U Active low peripheral reset output. This output is
D Reserved for future expansion. It has to be left
- PNX1700 main input clock. All internal clocks are
- Crystal oscillator output. Connect external crystal
derived from this 27 MHz input reference clock.
The crystal should be placed as close as possible
to the package. Refer to
board level connections.
This input follows the operating condition of
V
between this pin and XTAL_IN. Refer to
and
simple PNX1700 PCI configurations. It outputs a
33.23 MHz clock. A board level 27-33
resistor is recommended to reduce ringing.
input low triggers the hardware reset function of the
PNX1700 (including the JTAG state machine).
This pin can typically be connected to an on-board
reset upon voltage drop. It is active low. Upon
asserting this reset input, the PNX1700 asserts
SYS_RST_OUT_N to reset the attached peripheral
chips. This pin can also be tied to the PCI_RST
signal in PCI bus systems. This pin is 5 V tolerant
input.
triggers the hardware reset function of the
PNX1700 (This does not reset the JTAG state
machine). Upon asserting this reset input,
PNX1700 asserts SYS_RST_OUT_N to reset
attached peripheral chips. This pin can also be tied
to the PCI_RST signal in PCI bus systems.
With respect to the POR_IN_N reset pin, this pin
can be used has a warm reset. For most
applications, both reset pins can be tied together. it
is active low. This pin is 5 V tolerant input.
asserted upon any PNX1700 reset (hardware,
watchdog timer or software), and de-asserted by
PNX1700 system software. It is intended to be used
as a reset for external peripherals.
unconnected at the board level for normal
operation.
DD
.
Figure 28
Chapter 1: Integrated Circuit Data
for board level connections.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Figure 1
and
Figure 28
Figure 1
series
for
1-4
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