PNX1701EH,557 NXP Semiconductors, PNX1701EH,557 Datasheet - Page 238
PNX1701EH,557
Manufacturer Part Number
PNX1701EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1701EH557.pdf
(832 pages)
Specifications of PNX1701EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 13: Register Transfer/PIO Data Transfer on IDE
CS0,CS1,DA[2:0]
READ DD[15:0]
WRITE DD[15:0]
WRITE DD[7:0]/
READ DD[7:0]/
DIOR/DIOW
IORDY
Table 6: IDE Timing
PIO Timings (ATA-2 Spec)
t0
t1
t2
t2i
t3
t4
t5
t6
t6z
t9
trd
ta
tb
tc
•
During DMA transactions the high period is used for the setup of the first
transaction only.
Cycle time (min)
ADD valid to DIOR/DIOW setup (min)
DIOR/DIOW pulse width (min)
DIOR/DIOW Recovery time (min)
DIOW data setup (min)
DIOW data hold (min)
DIOR data setup (min)
DIOR data hold (min)
DIOR data tristate (max)
DIOR/DIOW to add, cs hold (min)
Read data valid to IORDY active (min)
IORDY setup time (max)
IORDY pulse width (max)
IORDY assertion to release (max)
t1
ta
Rev. 1 — 17 March 2006
t0
t2
tb
trd
t5
t3
t6
t4
tc
t9
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
t6z
Mode 0
600
70
165
-
60
30
50
5
30
20
0
35
1250
-
t2i
Chapter 7: PCI-XIO Module
PNX17xx Series
120
25
70
25
20
10
20
5
30
10
0
35
1250
5
Mode 4 (ns)
7-17
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