PNX1701EH,557 NXP Semiconductors, PNX1701EH,557 Datasheet - Page 756
PNX1701EH,557
Manufacturer Part Number
PNX1701EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1701EH557.pdf
(832 pages)
Specifications of PNX1701EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
3.2 Debug Settings
Transfer of Data to TM5250 via JTAG
Poll control register to check if input buffer is empty or not and scan in data when it is
empty and set the ifull control bit to 1 triggering an interrupt. Note that scanning in any
instruction automatically scans out the 3 least significant bits (including the ifull or
ofull bit) of the selected TM_DBG_CTRL register.
Table 3: Transfer of Data In via JTAG
Figure 2
PNX17xx Series system and a simplified block diagram of the PNX17xx Series
processor. The JTAG Interface Module, shown separately in the diagram, may be a
PC add-on card such as PC-1149.1/100F Boundary Scan Controller Board or a
similar module connected to a PC serial or parallel port. The JTAG interface module
is necessary for PNX17xx Series systems that are not plugged into a PC. For PC-
hosted PNX17xx Series systems, the host based TM5250 debugger front-end can
communicate with the target resident debug monitor via the PCI bus.
Enhancements to the standard JTAG functionality include a handshake mechanism
for transferring data to and from a PNX17xx Series processor’s MMIO registers,
support for posting an interrupt, and resetting processor state.
Action
IR shift in SEL_IFULL_IN instruction
While TM_DBG_CTRL2.ifull = 1, scan in SEL_IFULL_IN instruction
DR scan 33 bits of register TM_DBG_IFULL_IN
TOTAL
Figure 2:
shows an overview of the JTAG access path from a host machine to a target
System with JTAG Access
TM5250
CPU
JTAG
Connector
Controller
JTAG board
Rev. 1 — 17 March 2006
(such as a PC)
Host Machine
JTAG TAP (TCK, TMS, TDI, TDO)
D$
I$
Internal System Bus
MCU
Peripherals
Connection
Serial or Parallel
Scan Chain connecting possibly
other chips on board
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
JTAG Interface
Chapter 24: TM5250 Debug
May be a PC plug-in board
PNX17xx Series
Main
(SDRAM)
Memory
Module
Number of
TCK Cycles
12
11+
38
61+ cycles
24-6
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