PNX1701EH,557 NXP Semiconductors, PNX1701EH,557 Datasheet - Page 450
PNX1701EH,557
Manufacturer Part Number
PNX1701EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1701EH557.pdf
(832 pages)
Specifications of PNX1701EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 8: Relationship Between Input Formats and Data Capture
3. Register Descriptions
PNX17XX_SER_1
Preliminary data sheet
Video Modes
D1
VMI
RAW
HD
8-bit
10-bit
8-bit
8-bit
10-bit
8-bit
10-bit
2.5.8 Interrupt Generation
Single stream (YUV)
Video Data
X
X
X
3.1 Register Summary
The VIP contains a DVP-compliant interrupt generation mechanism. Interrupts can be
generated for the following events:
In addition to these interrupts, the VIP module also provides last-pixel-in signals, for
the VBI and video capture modes, to the GPIO block for timestamping.
The base address for VIP MMIO registers begins at absolute offset (with respect to
MMIO_BASE) of 0x10 6000.
Table 9: VIP MMIO Register Summary
Offset
0x10 6000
0x10 6020
0x10 6024
0x10 6040
0x10 6100
•
•
•
•
•
•
start of video
end of video (written to memory)
start of AUX in
end of AUX out (written to memory)
line threshold
pipeline error (due to illegal scaling ratio e.g. >2x scaling or memory bus
bandwidth error (fifo overflow))
Auxiliary Data
AUX
X
X
X
Name
VIP_MODE
ANC_DID_EVEN
ANC_DID_ODD
VIP_LINETHR
VIN_FORMAT
ANC
X
X
Rev. 1 — 17 March 2006
RAW
X
X
Description
VIP operation mode
ANC DID for even field
ANC DID for odd field
Video line count threshold
Video input format and mode
Dual stream (Y and U/V)
Video Data
X
X
X
Chapter 12: Video Input Processor
Auxiliary Data
AUX
X
X
X
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
ANC
RAW
X
X
12-19
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