TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 81
TXC-05802AIPQ
Manufacturer Part Number
TXC-05802AIPQ
Description
Manufacturer
Transwitch Corporation
Datasheet
1.TXC-05802AIPQ.pdf
(92 pages)
Specifications of TXC-05802AIPQ
Operating Supply Voltage (typ)
3.3/5V
Operating Temperature Classification
Industrial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
208
Lead Free Status / Rohs Status
Not Compliant
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OUTLET CELL FIFO SIZE AND LIMIT CONTROL REGISTERS
LOOPBACK CONTROL ADDRESS REGISTER
TRANSLATION RAM READ/WRITE CONTROL
Address
Address
Address
10
11
12
13
14
15
16
17
24
6-0
6-0
6-0
7-0
7-4
3-0
7-0
7-0
7-0
7-2
1-0
Bit
Bit
Bit
LBADDRU
CBRLIMIT
VBRLIMIT
LBADDRL
TRADATA
TRAMSB
CBRLEN
Symbol
Symbol
Symbol
TRAU
TRAL
--
--
Length, in cells, of the CBR section of the cell outlet FIFO. Valid val-
ues are zero through 89.
Congestion size for CBR FIFO. FECN may be set if CBR FIFO length
is greater than or equal to this value and IFECN = 1.
Congestion size for VBR FIFO. FECN may be set if VBR FIFO length
is greater than or equal to this value and IFECN = 1.
8 LSB of Loopback Routing Header, bits 11-4 of CellBus Bus Routing
Header (see Figure 31).
Reserved bits.
4 MSB of Loopback Routing Header, bits 15-12 of CellBus Bus Rout-
ing Header (see Figure 31).
8 LSB of the translation RAM address [pins TRA(7-0)].
Middle 8 bits of the translation RAM address [pins TRA(15-8)].
Data read from, or to be written into, the translation RAM at the
address defined by pins TRA(17-0) [pins TRD(7-0)].
Reserved bits.
2 MSB of the translation RAM address [pins TRA(17-16)]
- 81 -
Description
Description
Description
Ed. 3, November 1999
TXC-05802
CUBIT- Pro
TXC-05802-MB
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