TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 33

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

CUBIT- Pro
TXC-05802
THE CellBus BUS INTERFACE
Thirty-seven lines comprise the CellBus bus interface, as shown in Figure 2. There are thirty-two Data lines,
with Frame, Acknowledge, and Congestion Indicator lines, all sourced by a CUBIT- Pro device, and two Clock
lines sourced by external drivers.
Operation with Internal GTL Transceivers
Gunning Transceiver Logic (GTL) transceivers for CellBus bus Data, Frame, Acknowledge, and Congestion
Indicator lines are contained internally in the CUBIT- Pro , along with two clock line GTL receivers. Each of the
drivers has a maximum current sink capability of 48 mA and is capable of driving a bus on a card or on a back-
plane directly. Each of the GTL lines is to be pulled-up at each of its ends by a 50 ohm (+/- 5%) resistor (metal
film or carbon composition) to a +1.2 V low-impedance supply. Each end of each line should have a filtering
capacitor connected from the +1.2 V supply to ground, as shown in Figure 26.
+1.2V
+1.2V
0.01 F
0.01 F
50
50
CUBIT- Pro
CUBIT- Pro
CUBIT- Pro
Figure 26. External Circuit Requirements for GTL Transceivers
In the CUBIT- Pro pinout, all of the pins involved with the bus interface are aligned along one side of the pack-
age between pins 50 and 112. This side of the package must be aligned toward the board connector, or toward
the bus, with as little board trace length as possible between the pins and the connector or bus, to maximize
operating speed.
Clock Source
Two GTL-level clock signals must be driven to the CellBus bus from an external source. These are the write
clock, CBWC, and the read clock, CBRC. A phase relationship keeping the write clock between 0.5 and 4
nanoseconds behind the read clock is needed to ensure proper synchronous bus operation. When the clock
driver is driven from the center of the backplane (i.e., no greater than half a backplane length from any card) a
minimum phase distance of 0.5 ns or more must be maintained. When the driver is at one of the ends, a more
conservative 2-4 ns minimum is required. In any CellBus bus implementation, on the backplane and on each
card, care must be taken to ensure that these two lines are routed together. The capacitive and inductive load-
ings of the two lines should be as nearly equal as possible, to maintain performance. At the drive point, a delay
line should be used to maintain a stable delay, and the read and write clock drivers must be units of the same
integrated circuit package. All of these precautions will ensure the most stable clocks and permit the highest
possible operating speed.
Bus Arbiter Selection
One copy of the CellBus Bus Arbiter circuitry is included inside each CUBIT- Pro device. Enabling of the arbiter
on a particular CUBIT- Pro is done by connecting the ENARB pin of that device to ground (V
). Normally, one
SS
arbiter is turned on and the remaining arbiters on that bus are turned off. It is the responsibility of the overall
system control to decide which CUBIT- Pro will have its arbiter enabled, and to enable it. Failure of an arbiter
can be detected by using the NOGRT indications. If multiple CUBIT-Pros are indicating NOGRT failures, an
arbiter failure is indicated. It is again the responsibility of system control to enable another arbiter.
Upon switching from one arbiter to another, the receiving devices on the bus will automatically re-align to the
new frame position within one CellBus bus frame.
TXC-05802-MB
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Ed. 3, November 1999