TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 5

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

BLOCK DIAGRAM
A block diagram of the CUBIT- Pro device is shown in Figure 1. Further information on device operation and
the interfaces to external circuits is provided below in the following Operation section.
On the cell inlet side of the CUBIT- Pro is circuitry associated with accepting cells from the line and passing
them to the CellBus bus with an appropriate header. The Cell Inlet Port block is pin-selectable to be compliant
with either the ATM Forum UTOPIA (Universal Test and Operations Physical Interface for ATM) interface, a
TranSwitch 16-Bit interface, or the TranSwitch ALI-25 device interface. Incoming cells may carry a CellBus
Routing Header and translated outgoing VPI/VCI address, the translation function having been performed
externally, or this address translation and routing header insertion may be done by the CUBIT- Pro Translation
Control block. Translation and routing header tables to support this function are contained in an external static
RAM (up to 256k x 8 bits). They support VPI and/or VPI/VCI address translation. The incoming cells then pass
through a FIFO queue in the Inlet Queue block to the CellBus Bus Port via the CellBus Bus Interface Logic
block. When there is a cell in this 4-cell data cell queue, the CUBIT- Pro makes a bus access request, and
waits for a grant from the Bus Arbiter and Frame Pulse Generator block of the one CUBIT- Pro device attached
to the bus that has been enabled to perform these two functions. When a bus access grant is received, the
CUBIT- Pro sends the cell to the bus, in standard CellBus bus format. The cell can then be received by any con-
nected CUBIT- Pro or CUBIT-Pros. In addition to these incoming data cells, the CUBIT- Pro can also send Con-
trol cells from the local microprocessor to the bus via the Microprocessor Interface block. Special cells of
Loopback type received from the bus may also be returned to the bus, re-directed back to the CUBIT- Pro
which launched the original Loopback cell. Both the Control cells and the Loopback cells have 1-cell inlet
queues.
RData(7-0)
TData(7-0)
COD(7-0)/
COCLAV/
GFC(3-0)
CID(7-0)/
FRCABRCNG
CICLAV/
COSOC/
COENB/
COCLK/
RFlshD
CIENB/
CISOC/
CICLK/
RFlush
TDPrty
RdPrty
RLoad
RBClk
TLoad
RdVal
TBClk
CIF2/
TdVal
CIF1/
CIF4/
CIF3
EInt
8
4
8
Outlet
Inlet
Cell
Port
Cell
Port
LCLOCK
PHYEN
Synchronization FIFO
Address
A(7-0) D(7-0)
Translation
8
3 cells
Control
Figure 1. CUBIT- Pro TXC-05802 Block Diagram
Data
8
External Translation RAM Port
INT/
IRQ DTACK
Data TRD(7-0)
TRWE
Address TRA(17-0)
TROE
Microprocessor Interface
RDY/
Data Cell Queue
Control Queue
Loopback Queue
Loopback Queue
Data Cell Queue
Control Queue
4 cells
1 cell
1 cell
RD/WR
RD or WR
1 cell
4 cells
123
cells
- 5 -
Outlet Queue
Inlet Queue
SEL
PCLK
and Test
Reset
MOTO
6
Address
CONGOUT
Screen
Cell
CBDISABLE
Generator
Interface
CellBus
Arbiter
Frame
Logic
Pulse
Bus
Bus
and
12
VREF
Other Controls
ENARB
Ed. 3, November 1999
CellBus Bus Port
TXC-05802
CUBIT- Pro
TXC-05802-MB
32
CBD(31-0)
CBRC
CBWC
CBF
CBACK
CBCONG