TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 77

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TXC-05802AIPQ

Manufacturer Part Number
TXC-05802AIPQ
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-05802AIPQ

Operating Supply Voltage (typ)
3.3/5V
Operating Temperature Classification
Industrial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
208
Lead Free Status / Rohs Status
Not Compliant
MEMORY MAP DESCRIPTIONS
DEVICE DESCRIPTOR AND RESET BITS
* All addresses in memory map description tables are hexadecimal. Reserved addresses are not listed.
STATUS AND INTERRUPT-ENABLE BITS
Address
Address *
00-02
05
06
03
03
04
07
5, 4
Bit
5,4
7
6
3
2
1
0
7
6
3
2
1
0
7-0
3-0
7-4
7-4
3-0
7-1
Bit
0
CBLOWC
INTENA7
INTENA6
INTENA3
INTENA2
INTENA1
INTENA0
CBLORC
Symbol
CTNAK
CTACK
CBLOF
BIP-8
Symbol
RESET
DEVID
--
--
--
--
Bit is set to 1 if a microprocessor control cell sent by the CUBIT- Pro is
not accepted at destination
Bit is set to 1 if a microprocessor control cell sent by the CUBIT- Pro is
accepted at destination
Reserved bits.
Bit is set to 1 when a BIP-8 error is detected in the receiver. It will gen-
erate a microprocessor interrupt if bit 3 (INTENA3) is set to one in the
interrupt enable location at address 06H.
Bit is set to 1 if the CellBus bus frame pulse is not present for two con-
secutive frame pulse times (U32 = low) or four consecutive frame
pulse times (U32 = high).
Bit is set to 1 if the CellBus bus read clock is not present for more than
the equivalent of 32 PCLK cycles.
Bit is set to 1 if the CellBus bus write clock is not present for more than
the equivalent of 32 PCLK cycles.
Interrupt enabled for CTNAK, if = 1.
Interrupt enabled for CTACK, if = 1.
Reserved bits.
Interrupt enabled for BIP-8, if = 1.
Interrupt enabled for CBLOF, if = 1.
Interrupt enabled for CBLORC, if = 1.
Interrupt enabled for CBLOWC, if = 1.
Device identification code (28 bits).
Version number.
Mask revision level.
Reserved bits.
Reserved bits.
When set to 1, this bit clears the counters DISCCTR, MRCCTR,
HECERCTR and INCELL (L, M and U) in addresses 18H through
1DH. This bit clears to 0 automatically.
- 77 -
Description
Description
Ed. 3, November 1999
TXC-05802
CUBIT- Pro
TXC-05802-MB

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