TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 68

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

CellBus Bus Port
Note:
The CUBIT- Pro CellBus write clock to CellBus data out time delay is complex and highly dependent on loading. The minimum
value of delay t
table as 6 ns and is guaranteed by design inside the CUBIT- Pro . The maximum value (over voltage, temperature and process
ranges) of t
a 1.0 pF capacitor to ground. These output delay numbers have two components, internal delay and GTL output delay. With a real
system load, the value of the GTL driver output delay of the CUBIT- Pro VLSI chip will depend on external circuitry: chip package
effects, printed circuit boards at both ends, connectors, and backplane traces. The in-circuit value of delay then must be derived
by adding the delays arising from these external effects to the internal delay.
TranSwitch strongly recommends that all CellBus applications be analyzed by analog circuit simulation, using such tools as
HSpice
Pro data delay time is divided into two parts: an internal delay time from the CBWC input to the (internal) GTL driver input, and the
GTL driver delay. The minimum and maximum values of the CUBIT- Pro internal delay (up to the GTL driver) are 4.5 ns and 12 ns,
respectively. In general, these simulations model timing from one CUBIT- Pro , through various levels of system interconnect, to
another CUBIT- Pro . Models generally include the effects of the device package, printed circuit board and connectors, and back-
plane. This level of simulation can very effectively model system performance. The actual value of delay from a CUBIT- Pro CBWC
input to the point modeled in the simulation is the sum of the simulation delay and the CUBIT- Pro internal delay.
Applications with backplanes up to 17 inches wide and having clock speeds of no more than 25 MHz have proven to work well
with good basic design. For the most part, this means keeping all of the significant copper wiring traces short: those from the back-
plane connector to the CUBIT- Pro , and those from the CellBus bus ends to the pull-up resistors. Grounding is similarly important
to performance, with the working assumption being that the backplane and all plug-in cards use full planes for power and ground,
to maintain very low ground and supply inductance. The GTL clocks in this case are bussed across the backplane to all cards and
driven at any point by a Texas Instruments SN74GTL1655, or equivalent. The clock line pull-ups are 27 ohms at each end. The
delay from CBWC to CBRC is maintained, by an analog delay line at the clock source point, at a value between 2 and 4 ns.
Please contact the TranSwitch Applications Engineering Department for additional information and support.
HSpice is a registered trademark of Meta-Software, Inc.
CellBus bus inputs setup time before
CBRC
CellBus bus inputs hold time after CBRC
CellBus bus outputs delay after CBWC
®
. TranSwitch can provide the HSpice model of the CUBIT- Pro GTL transceiver. When doing such modeling, the CUBIT-
Data inputs from bus
D(1)
Data outputs to bus
CBRC
(Input)
CBWC
(Input)
D(1)
is 15.8 ns low-to-high, and 14.1 ns high-to-low for a minimum load consisting of a 50 ohm resistor to +1.2 volts and
CBD(31-0)
CBF
CBACK
CBCONG
CBD(31-0)
CBF
CBACK
CBCONG
Parameter
is the time after CBWC going low for which the old data output value does not change. This is shown in the
Figure 48. CellBus Bus Timing
t
Symbol
SU(1)
t
t
t
SU(1)
H(1)
D(1)
t
D(1)
- 68 -
t
H(1)
Min
0.0
6.0
6.0
Typ
See note
Max
Ed. 3, November 1999
TXC-05802
CUBIT- Pro
TXC-05802-MB
Unit
ns
ns
ns