TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 53

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TXC-05802AIPQ

Manufacturer Part Number
TXC-05802AIPQ
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-05802AIPQ

Operating Supply Voltage (typ)
3.3/5V
Operating Temperature Classification
Industrial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
208
Lead Free Status / Rohs Status
Not Compliant
Note: TRWE output is high. All timing parameter values apply to both Microprocessor and Translation RAM read cycles.
TROE output delay after CICLK (PHY Mode)
TROE output delay after PCLK
TROE output delay after LCLOCK
TROE output delay after CBWC
TRA(17-0) output delay after CICLK
TRA(17-0) output delay after PCLK
TRA(17-0) output delay after LCLOCK
TRA(17-0) output delay after CBWC
TRD(7-0) setup time before CICLK
TRD(7-0) setup time before PCLK
TRD(7-0) setup time before LCLOCK
TRD(7-0) setup time before CBWC
TRD(7-0) hold time after CICLK
TRD(7-0) hold time after PCLK
TRD(7-0) hold time after LCLOCK
TRD(7-0) hold time after CBWC
CICLK
(Input)
(Input)
LCLOCK
(Input)
CBWC
TROE
(Output)
TRA(17-0)
(Output)
PCLK
(Input)
TRD(7-0)
(Input)
Parameter
t
D(1a)
t
t
t
t
t
D(2a)
D(1b)
D(2b)
D(2c)
D(1c)
Figure 33. Translation RAM Timing - Read from RAM
directed read cycle
Microprocessor-
from RAM
t
SU(1d)
t
t
SU(1a)
t
SU(1b)
SU(1c)
t
D(1d)
t
D(2d)
Data
Valid
t
t
t
- 53 -
H(1b)
H(1a)
H(1c)
t
H(1d)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
SU(1a)
SU(1b)
SU(1c)
SU(1d)
t
t
t
t
D(1a)
D(1b)
D(1c)
D(1d)
D(2a)
D(2b)
D(2c)
D(2d)
H(1a)
H(1b)
H(1c)
H(1d)
Translation RAM read cycle
Min
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
1.0
1.0
1.0
1.0
6.0
6.0
6.0
11
Data
Valid
Typ
Data
Valid
Max
Ed. 3, November 1999
14
16
14
20
16
16
16
21
TXC-05802
CUBIT- Pro
TXC-05802-MB
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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