ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 73
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ISP1564HLUM
Manufacturer Part Number
ISP1564HLUM
Description
Manufacturer
STEricsson
Datasheet
1.ISP1564HLUM.pdf
(100 pages)
Specifications of ISP1564HLUM
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Compliant
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Table 110. ASYNCLISTADDR - Current Asynchronous List Address register bit allocation
Address: Content of the base address register + 38h
[1]
Table 111. ASYNCLISTADDR - Current Asynchronous List Address register bit description
Address: Content of the base address register + 38h
Table 112. CONFIGFLAG - Configure Flag register bit allocation
Address: Content of the base address register + 60h
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 12
11 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits must always be written with the reset value.
11.3.7 CONFIGFLAG register
Symbol
LPL[19:0]
reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
31
23
15
31
23
15
0
0
0
7
0
0
0
0
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in
Description
Link Pointer List: These bits correspond to memory address signals 31 to 12, respectively.
This field may only reference a Queue Head (QH).
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
30
22
14
30
22
14
0
0
0
6
0
0
0
0
LPL[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
29
21
13
29
21
13
0
0
0
5
0
0
0
0
Rev. 01 — 4 December 2006
R/W
R/W
R/W
R/W
R/W
R/W
R/W
28
20
12
28
20
12
0
0
0
4
0
0
0
0
LPL[19:12]
reserved
reserved
reserved
reserved
LPL[11:4]
[1]
[1]
[1]
[1]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
27
19
11
27
19
11
0
0
0
3
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
26
18
10
26
18
10
0
0
0
2
0
0
0
0
HS USB PCI Host Controller
reserved
[1]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
25
17
25
17
0
0
9
0
1
0
0
0
9
0
© NXP B.V. 2006. All rights reserved.
ISP1564
Table
R/W
R/W
R/W
R/W
R/W
R/W
R/W
112.
24
16
24
16
0
0
8
0
0
0
0
0
8
0
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