ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 72

• Manufacturer Part Number: ISP1564HLUM
• Manufacturer: STEricsson

Specifications of ISP1564HLUM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 108. PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation
Address: Content of the base address register + 34h
[1]
Table 109. PERIODICLISTBASE - Periodic Frame List Base Address register bit description
Address: Content of the base address register + 34h
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 12
11 to 0
The reserved bits must always be written with the reset value.
Symbol
BA[19:0]
reserved
11.3.6 ASYNCLISTADDR register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
system software loads this register before starting the schedule execution by the Host
Controller. The memory structure referenced by this physical memory pointer is assumed
as 4 kB aligned. The contents of this register are combined with the FRINDEX register to
enable the Host Controller to step through the periodic frame list in sequence.
The bit allocation is given in
This 32-bit register contains the address of the next asynchronous queue head to be
executed. If the Host Controller is in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of
the HCCPARAMS register), the most significant 32 bits of every control data structure
address comes from the CTRLDSSEGMENT register. For details on the
CTRLDSSEGMENT register, refer to Enhanced Host Controller Interface Specification for
Universal Serial Bus Rev. 1.0 . Bits 4 to 0 of this register always return zeros when read.
The memory structure referenced by the physical memory pointer is assumed as 32 bytes
(cache aligned). For bit allocation, see
Description
Base Address: These bits correspond to memory address signals 31 to 12, respectively.
-
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
BA[3:0]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 4 December 2006
Table
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
108.
reserved
BA[19:12]
BA[11:4]
Table
[1]
R/W
R/W
R/W
R/W
27
19
11
110.
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
reserved
[1]
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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