ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 44

• Manufacturer Part Number: ISP1564HLUM
• Manufacturer: STEricsson

Specifications of ISP1564HLUM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 58.
Address: Content of the base address register + 10h
Table 59.
Address: Content of the base address register + 14h
[1]
ISP1564_1
Product data sheet
Bit
2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits must always be written with the reset value.
Symbol
SF
WDH
SO
HcInterruptEnable - Host Controller Interrupt Enable register bit description
HcInterruptDisable - Host Controller Interrupt Disable register bit allocation
11.1.6 HcInterruptDisable register
reserved
R/W
R/W
R/W
R/W
MIE
31
23
15
0
0
0
7
0
[1]
Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the
HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the
corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this
register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a
read, the current value of the HcInterruptEnable register is returned.
The register contains 4 bytes, and the bit allocation is given in
Description
Start-of-Frame:
0 — Ignore
1 — Enables interrupt generation because of Start-of-Frame.
HcDoneHead Write-back:
0 — Ignore
1 — Enables interrupt generation because of HcDoneHead write-back.
Scheduling Overrun:
0 — Ignore
1 — Enables interrupt generation because of scheduling overrun.
RHSC
R/W
R/W
R/W
R/W
OC
30
22
14
0
0
0
6
0
FNO
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 4 December 2006
R/W
R/W
R/W
R/W
UE
28
20
12
0
0
0
4
0
reserved
reserved
[1]
[1]
R/W
R/W
R/W
R/W
RD
27
19
11
0
0
0
3
0
reserved
[1]
R/W
R/W
R/W
R/W
SF
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
…continued
Table
WDH
59.
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
R/W
SO
24
16
0
0
8
0
0
0
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