ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 50

• Manufacturer Part Number: ISP1564HLUM
• Manufacturer: STEricsson

Specifications of ISP1564HLUM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
[1]
Table 72.
Address: Content of the base address register + 2Ch
Table 73.
Address: Content of the base address register + 30h
[1]
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits must always be written with the reset value.
The reserved bits must always be written with the reset value.
Symbol
BCED[27:0]
reserved
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description
HcDoneHead - Host Controller Done Head register bit allocation
11.1.13 HcDoneHead register
R/W
R/W
R/W
R/W
R/W
31
23
15
7
0
0
0
0
7
0
Description
Bulk Current ED: This is advanced to the next ED after the Host Controller has served the current
ED. The Host Controller continues processing the list from where it left off in the last frame. When it
reaches the end of the bulk list, the Host Controller checks CLF (bit 1 of HcCommandStatus). If the
CLF bit is not set, nothing is done. If the CLF bit is set, it copies the content of HcBulkHeadED to
HcBulkCurrentED and clears the CLF bit. The HCD can modify this register only when BLE (bit 5 in
the HcControl register) is cleared. When HcControl is set, the HCD reads the instantaneous value
of this register. This is initially set to logic 0 to indicate the end of the bulk list.
-
The HcDoneHead register contains the physical address of the last completed TD that
was added to the done queue. In a normal operation, the HCD need not read this register
because its content is periodically written to the HCCA.
of the register.
R/W
R/W
R/W
R/W
R/W
30
22
14
6
0
0
0
0
6
0
BCED[3:0]
DH[3:0]
R/W
R/W
R/W
R/W
R/W
29
21
13
5
0
0
0
0
5
0
Rev. 01 — 4 December 2006
R/W
R/W
R/W
R/W
R/W
28
20
12
4
0
0
0
0
4
0
DH[27:20]
DH[19:12]
DH[11:4]
R/W
R/W
R/W
R/W
R/W
27
19
11
3
0
0
0
0
3
0
Table 73
R/W
R/W
R/W
R/W
R/W
26
18
10
2
0
0
0
0
2
0
HS USB PCI Host Controller
reserved
reserved
contains the bit allocation
[1]
[1]
R/W
R/W
R/W
R/W
R/W
25
17
1
0
0
0
9
0
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
R/W
R/W
24
16
0
0
0
0
8
0
0
0
49 of 99