ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 47
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ISP1564HLUM
Manufacturer Part Number
ISP1564HLUM
Description
Manufacturer
STEricsson
Datasheet
1.ISP1564HLUM.pdf
(100 pages)
Specifications of ISP1564HLUM
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Compliant
Available stocks
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NXP Semiconductors
Table 64.
Address: Content of the base address register + 1Ch
Table 65.
Address: Content of the base address register + 20h
Table 66.
Address: Content of the base address register + 20h
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4 CHED[27:0] Control Head ED: The Host Controller traverses the control list, starting with the HcControlHeadED
3 to 0
Symbol
reserved
Symbol
PCED[27:0]
reserved
HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description
HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation
HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit description
11.1.9 HcControlHeadED register
31
23
15
R
R
R
R
R
7
0
0
0
0
7
0
Description
pointer. The content is loaded from HCCA during the initialization of the Host Controller.
-
The HcControlHeadED register contains the physical address of the first ED of the control
list. The bit allocation is given in
Description
Period Current ED: This is used by the Host Controller to point to the head of one of the periodic
lists that must be processed in the current frame. The content of this register is updated by the
Host Controller after a periodic ED is processed. The HCD may read the content in determining
which ED is being processed at the time of reading.
-
30
22
14
R
R
R
R
R
6
0
0
0
0
6
0
PCED[3:0]
CHED[3:0]
29
21
13
R
R
R
R
R
5
0
0
0
0
5
0
Rev. 01 — 4 December 2006
28
20
12
R
Table
R
R
R
R
4
0
0
0
0
4
0
CHED[27:20]
CHED[19:12]
CHED[11:4]
65.
27
19
11
R
R
R
R
R
3
0
0
0
0
3
0
26
18
10
R
R
R
R
R
2
0
0
0
0
2
0
HS USB PCI Host Controller
reserved
reserved
25
17
R
R
R
R
R
1
0
0
0
9
0
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
24
16
R
R
R
R
R
0
0
0
0
8
0
0
0
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