ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 48

• Manufacturer Part Number: ISP1564HLUM
• Manufacturer: STEricsson

Specifications of ISP1564HLUM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 67.
Address: Content of the base address register + 24h
Table 68.
Address: Content of the base address register + 24h
Table 69.
Address: Content of the base address register + 28h
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit description
HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation
Symbol
CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving the present. The Host
reserved
11.1.10 HcControlCurrentED register
11.1.11 HcBulkHeadED register
R/W
31
23
15
31
R
R
R
R
0
0
0
7
0
0
The HcControlCurrentED register contains the physical address of the current ED of the
control list. The bit allocation is given in
This register (see
Description
Controller must continue processing the list from where it left in the last frame. When it reaches
the end of the control list, the Host Controller checks CLF (bit 1 of HcCommandStatus). If set, it
copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it
does nothing. The HCD is allowed to modify this register only when CLE (bit 4 in the HcControl
register) is cleared. When set, the HCD only reads the instantaneous value of this register.
Initially, this is set to logic 0 to indicate the end of the control list.
-
R/W
30
22
14
30
R
R
R
R
0
0
0
6
0
0
CCED[3:0]
Table
R/W
29
21
13
29
R
R
R
R
0
0
0
5
0
0
Rev. 01 — 4 December 2006
69) contains the physical address of the first ED of the bulk list.
R/W
28
20
12
28
R
R
R
R
0
0
0
4
0
0
CCED[27:20]
CCED[19:12]
BHED[27:20]
CCED[11:4]
Table
R/W
27
19
11
27
R
R
R
R
0
0
0
3
0
0
67.
R/W
26
18
10
26
R
R
R
R
0
0
0
2
0
0
HS USB PCI Host Controller
reserved
R/W
25
17
25
R
R
R
R
0
0
9
0
1
0
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
24
16
24
R
R
R
R
0
0
8
0
0
0
0
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