ADC12H034CIMSA/NOPB National Semiconductor, ADC12H034CIMSA/NOPB Datasheet - Page 36

• Manufacturer Part Number: ADC12H034CIMSA/NOPB
• Description: ADC 12BIT W/S&H +SIGN 24-SSOP
• Manufacturer: National Semiconductor

Specifications of ADC12H034CIMSA/NOPB

• Number Of Bits: 12
• Data Interface: NSC MICROWIRE™, Serial
• Number Of Converters: 4
• Power Dissipation (max): 33mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP (0.200", 5.30mm Width)
• Number Of Elements: 1
• Architecture: SAR
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 500mW
• Differential Linearity Error: ±1LSB
• Integral Nonlinearity Error: ±1LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC12H034CIMSA

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capacitors should be located as close to the bypassed pin as
practical, especially the smaller value capacitors.
11.0 CLOCK SIGNAL LINE ISOLATION
The ADC12030/2/4/8's performance is optimized by routing
the analog input/output and reference signal conductors as
far as possible from the conductors that carry the clock signals
to the CCLK and SCLK pins. Maintaining a separation of at
least 7 to 10 times the height of the clock trace above its ref-
erence plane is recommended.
12.0 THE CALIBRATION CYCLE
A calibration cycle needs to be started after the power sup-
plies, reference, and clock have been given enough time to
stabilize after initial turn-on. During the calibration cycle, cor-
rection values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale, off-
set, and linearity errors down to the specified limits. Full-scale
error typically changes ±0.4 LSB over temperature and lin-
earity error changes even less; therefore it should be neces-
sary to go through the calibration cycle only once after power
up if the Power Supply Voltage and the ambient temperature
do not change significantly (see the curves in the Typical Per-
formance Characteristics).
13.0 THE Auto Zero CYCLE
To correct for any change in the zero (offset) error of the ADC,
the Auto Zero cycle can be used. It may be necessary to do
an Auto Zero cycle whenever the ambient temperature or the
power supply voltage change significantly. (See the curves
titled “Offset or Zero Error Change vs. Ambient Temperature”
and “Offset or Zero Error Change vs. Supply Voltage” in the
Typical Performance Characteristics.)
14.0 DYNAMIC PERFORMANCE
Many applications require the converter to digitize AC signals,
but the standard DC integral and differential nonlinearity
specifications will not accurately predict the ADC's perfor-
mance with AC input signals. The important specifications for
Note: V
A
+
, V
D
+
, and V
REF
+
on the ADC12038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF caps.
36
AC applications reflect the converter's ability to digitize AC
signals without significant spectral errors and without adding
noise to the digitized signal. Dynamic characteristics such as
signal-to-noise (S/N), signal-to-noise + distortion ratio
(S/(N + D)), effective bits, full power bandwidth, aperture time
and aperture jitter are quantitative measures of the ADC's ca-
pability.
An ADC's AC performance can be measured using Fast
Fourier Transform (FFT) methods. A sinusoidal waveform is
applied to the ADC's input, and the transform is then per-
formed on the digitized waveform. S/(N + D) and S/N are
calculated from the resulting FFT data, and a spectral plot
may also be obtained. Typical values for S/N are shown in the
table of Electrical Characteristics, and spectral plots of
S/(N + D) are included in the typical performance curves.
The ADC's noise and distortion levels will change with the
frequency of the input signal, with more distortion and noise
occurring at higher signal frequencies. This can be seen in
the S/(N + D) versus frequency curves.
Effective number of bits can also be useful in describing the
ADC's noise and distortion performance. An ideal ADC will
have some amount of quantization noise, determined by its
resolution, and no distortion, which will yield an optimum
S/(N + D) ratio given by the following equation:
where "n" is the ADC's resolution in bits.
The effective bits of an actual ADC is found to be:
As an example, this device with a differential signed 5V, 1 kHz
sine wave input signal will typically have a S/(N + D) of 77 dB,
which is equivalent to 12.5 effective bits.
15.0 AN RS232 SERIAL INTERFACE
Shown on the following page is a schematic for an RS232
interface to any IBM and compatible PCs. The DTR, RTS, and
CTS RS232 signal lines are buffered via level translators and
connected to the ADC12038's DI, SCLK, and DO pins, re-
spectively. The D flip flop drives the CS control line.
n(effective) = ENOB = (S/(N + D) - 1.76 / 6.02
S/(N + D) = (6.02 × n + 1.76) dB
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