IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 93
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IDT82V3280PFG
Manufacturer Part Number
IDT82V3280PFG
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280PFG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280PFG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3280PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V3280PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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PRE_DIV_CH_CNFG - DivN Divider Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1
Programming Information
IDT82V3280
Address: 23H
Type: Read / Write
Default Value: XXXX0000
Address: 24H
Type: Read / Write
Default Value: 00000000
PRE_DIVN_VA
7 - 4
3 - 0
7 - 0
7
-
Bit
Bit
LUE7
7
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H).
6
-
PRE_DIVN_VA
Name
Name
LUE6
-
6
5
-
4
-
PRE_DIVN_VA
Reserved.
This register is an indirect address register for Register 24H and 25H.
These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the
selected input clock.
0000: Reserved. (default)
0001, 0010: Reserved.
0011: IN3.
0100: IN4.
......
1101: IN13.
1110: IN14.
1111: Reserved.
LUE5
5
PRE_DIV_CH_VALUE3
3
PRE_DIVN_VA
LUE4
4
93
PRE_DIV_CH_VALUE2
PRE_DIVN_VA
LUE3
3
2
Description
Description
PRE_DIVN_VA
PRE_DIV_CH_VALUE1
LUE2
2
1
PRE_DIVN_VA
LUE1
1
PRE_DIV_CH_VALUE0
December 9, 2008
PRE_DIVN_VA
0
LUE0
WAN PLL
0
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