IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 147

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2
Programming Information
IDT82V3280
Address:7BH
Type: Read / Write
Default Value: 0XXXXX00
PH_OFFSET_E
6 - 2
1 - 0
Bit
7
N
7
PH_OFFSET_EN
PH_OFFSET[9:8]
Name
-
6
-
This bit determines whether the input-to-output phase offset is enabled.
If the device is configured as the Master, the input-to-output phase offset:
0: Disabled. (default)
1: Enabled.
If the device is configured as the Slave, the input-to-output phase offset is always enabled.
Reserved.
These bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the input-to-output phase offset in ns
to adjust will be gotten.
5
-
4
-
147
3
-
Description
2
-
PH_OFFSET9
1
December 9, 2008
PH_OFFSET8
0
WAN PLL