IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 6

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

List of Tables
Table 1: Pin Description ............................................................................................................................................................................................. 13
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 19
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 20
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 22
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 24
Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 25
Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 25
Table 8: External Fast Selection ................................................................................................................................................................................ 25
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 26
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 27
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 27
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 28
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 29
Table 14: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 30
Table 15: T0 DPLL Operating Mode Control ............................................................................................................................................................... 31
Table 16: T4 DPLL Operating Mode Control ............................................................................................................................................................... 33
Table 17: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 33
Table 18: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 34
Table 19: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 35
Table 20: Holdover Frequency Offset Read ................................................................................................................................................................ 35
Table 21: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 36
Table 22: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 38
Table 23: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 39
Table 24: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 40
Table 25: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 APLL .............................................................................................................................. 41
Table 26: Outputs on OUT8 & OUT9 ........................................................................................................................................................................... 41
Table 27: Synchronization Control ............................................................................................................................................................................... 42
Table 28: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 43
Table 29: Device Master / Slave Control ..................................................................................................................................................................... 44
Table 30: Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 45
Table 31: Microprocessor Interface ............................................................................................................................................................................. 48
Table 32: Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 49
Table 33: Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 50
Table 34: Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 51
Table 35: Read Timing Characteristics in Intel Mode .................................................................................................................................................. 52
Table 36: Write Timing Characteristics in Intel Mode .................................................................................................................................................. 53
Table 37: Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 54
Table 38: Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 55
Table 39: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 56
Table 40: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 57
Table 41: JTAG Timing Characteristics ....................................................................................................................................................................... 58
Table 42: Register List and Map .................................................................................................................................................................................. 59
Table 43: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 149
Table 44: Thermal Data ............................................................................................................................................................................................. 149
Table 45: Absolute Maximum Rating ......................................................................................................................................................................... 151
Table 46: Recommended Operation Conditions ........................................................................................................................................................ 151
Table 47: AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 153
Table 48: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 154
List of Tables
6
December 9, 2008