IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 133
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IDT82V3280PFG
Manufacturer Part Number
IDT82V3280PFG
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280PFG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280PFG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3280PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V3280PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 *
DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1
Programming Information
Address: 65H
Type: Read / Write
Default Value: 10001100
IDT82V3280
Address: 64H
Type: Read
Default Value: 00000000
Address: 66H
Type: Read / Write
Default Value: 10101011
DPLL_FREQ_H
FREQ_LIMT_P
CURRENT_DP
LL_FREQ23
6 - 0
ARD_LIMT7
7 - 0
Bit
7 - 0
Bit
7
Bit
H_LOS
7
7
7
DPLL_FREQ_SOFT_LIMT[6:0]
CURRENT_DPLL_FREQ[23:16]
DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H).
FREQ_LIMT_PH_LOS
CURRENT_DP
DPLL_FREQ_S
DPLL_FREQ_H
LL_FREQ22
OFT_LIMT6
ARD_LIMT6
Name
Name
6
6
6
Name
CURRENT_DP
DPLL_FREQ_S
DPLL_FREQ_H
LL_FREQ21
OFT_LIMT5
ARD_LIMT5
This bit determines whether the T0/T4 DPLL in hard alarm status will result in it unlocked.
0: Disabled.
1: Enabled. (default)
These bits represent an unsigned integer. If the value is multiplied by 0.724, the DPLL soft limit for T0 and T4 paths in
ppm will be gotten.
The DPLL soft limit is symmetrical about zero.
The CURRENT_DPLL_FREQ[23:0] bits represent a 2’s complement signed integer. If the value in these bits is mul-
tiplied by 0.000011, the current frequency offset of the T0/T4 DPLL output in ppm with respect to the master clock
will be gotten.
5
5
5
CURRENT_DP
DPLL_FREQ_S
DPLL_FREQ_H
LL_FREQ20
ARD_LIMT4
OFT_LIMT4
4
4
4
133
CURRENT_DP
DPLL_FREQ_S
DPLL_FREQ_H
LL_FREQ19
OFT_LIMT3
ARD_LIMT3
3
3
3
Description
Description
Description
CURRENT_DP
DPLL_FREQ_S
DPLL_FREQ_H
LL_FREQ18
OFT_LIMT2
ARD_LIMT2
2
2
2
CURRENT_DP
DPLL_FREQ_S
DPLL_FREQ_H
LL_FREQ17
ARD_LIMT1
OFT_LIMT1
1
1
1
December 9, 2008
DPLL_FREQ_S
DPLL_FREQ_H
CURRENT_DP
LL_FREQ16
ARD_LIMT0
OFT_LIMT0
0
0
0
WAN PLL
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