IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 3

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

FEATURES .............................................................................................................................................................................. 9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11
1 PIN ASSIGNMENT ........................................................................................................................................................... 12
2 PIN DESCRIPTION .......................................................................................................................................................... 13
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 19
Table of Contents
3.1 RESET ........................................................................................................................................................................................................... 19
3.2 MASTER CLOCK .......................................................................................................................................................................................... 19
3.3 INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 20
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 21
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 23
3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 25
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 27
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 29
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 31
3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 34
HIGHLIGHTS.................................................................................................................................................................................................... 9
MAIN FEATURES ............................................................................................................................................................................................ 9
OTHER FEATURES ......................................................................................................................................................................................... 9
3.3.1
3.3.2
3.5.1
3.5.2
3.5.3
3.6.1
3.6.2
3.6.3
3.7.1
3.7.2
3.7.3
3.8.1
3.8.2
3.8.3
3.9.1
3.9.2
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 34
Input Clocks .................................................................................................................................................................................... 20
Frame SYNC Input Signals ............................................................................................................................................................ 20
LOS Monitoring .............................................................................................................................................................................. 23
Activity Monitoring ......................................................................................................................................................................... 23
Frequency Monitoring ................................................................................................................................................................... 24
External Fast Selection (T0 only) .................................................................................................................................................. 25
Forced Selection ............................................................................................................................................................................ 26
Automatic Selection ....................................................................................................................................................................... 26
T0 / T4 DPLL Locking Detection ................................................................................................................................................... 27
3.7.1.1
3.7.1.2
3.7.1.3
3.7.1.4
Locking Status ............................................................................................................................................................................... 27
Phase Lock Alarm (T0 only) .......................................................................................................................................................... 28
Input Clock Validity ........................................................................................................................................................................ 29
Selected Input Clock Switch ......................................................................................................................................................... 29
3.8.2.1
3.8.2.2
Selected / Qualified Input Clocks Indication ................................................................................................................................ 30
T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31
T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 33
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 34
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 34
3.10.1.3 Locked Mode .................................................................................................................................................................... 34
Fast Loss .......................................................................................................................................................................... 27
Coarse Phase Loss .......................................................................................................................................................... 27
Fine Phase Loss ............................................................................................................................................................... 27
Hard Limit Exceeding ....................................................................................................................................................... 27
Revertive Switch ............................................................................................................................................................... 29
Non-Revertive Switch (T0 only) ........................................................................................................................................ 30
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Table of Contents
December 9, 2008