IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 111

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

IN5_IN6_STS - Input Clock 5 & 6 Status
Programming Information
IDT82V3280
Address: 45H
Type: Read
Default Value: X110X110
Bit
7
6
5
4
3
2
1
0
7
-
IN6_FREQ_HAR
IN6_NO_ACTIVITY_ALARM
IN5_NO_ACTIVITY_ALARM
IN6_FREQ_HARD_ALARM
IN5_FREQ_HARD_ALARM
D_ALARM
IN6_PH_LOCK_ALARM
IN5_PH_LOCK_ALARM
6
Name
-
-
IN6_NO_ACTIVI
TY_ALARM
5
Reserved.
This bit indicates whether IN6 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN6 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN6 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second ) which starts from when the alarm is raised.
Reserved.
This bit indicates whether IN5 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN5 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN5 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second ) which starts from when the alarm is raised.
IN6_PH_LOCK_
ALARM
4
111
3
-
IN5_FREQ_HAR
Description
D_ALARM
2
IN5_NO_ACTIVI
TY_ALARM
1
December 9, 2008
IN5_PH_LOCK_
ALARM
0
WAN PLL