IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 32
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IDT82V3280PFG
Manufacturer Part Number
IDT82V3280PFG
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280PFG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280PFG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3280PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V3280PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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Functional Description
IDT82V3280
Notes to
1. Reset.
2. An input clock is selected.
3. The T0 selected input clock is disqualified AND No qualified input clock is available.
4. The T0 selected input clock is switched to another one.
5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
6. The T0 selected input clock is disqualified AND No qualified input clock is available.
7. The T0 selected input clock is unlocked (the T0_DPLL_LOCK bit is ‘0’).
8. The T0 selected input clock is locked again (the T0_DPLL_LOCK bit is ‘1’).
9. The T0 selected input clock is switched to another one.
10. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
11. The T0 selected input clock is disqualified AND No qualified input clock is available.
12. The T0 selected input clock is switched to another one.
13. The T0 selected input clock is disqualified AND No qualified input clock is available.
14. An input clock is selected.
15. The T0 selected input clock is switched to another one.
Figure
7:
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode
15
Pre-Locked2
mode
4
10
Pre-Locked
mode
9
12
1
3
5
8
Lost-Phase
32
Locked
mode
mode
Free-Run mode
2
7
13
11
6
14
Holdover
mode
December 9, 2008
WAN PLL
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