PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 525

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
C.4.9
The TCS compiler supports the loading of instruction in
memory differently for Big Endian and Little Endian
modes.
C.5
PNX1300 is required to operate in the same endian-ness
as the host CPU. At reset, PNX1300 operates in Big En-
dian mode; no special steps are required to set the Endi-
an bits. When using PNX1300 in Little Endian systems,
Figure C-14. VLD input and output data format
Run level output
Run value = 0x1234
Level value = 0x5678
Header output
Header = 0x12345678
Input data
At word Address A
SUMMARY
Compiler
Byte
A+3
A+3
A+3
78
78
n+3
Byte
Big Endian Mode
A+2
A+2
A+2
56
56
n+2
Byte
A+1
A+1
A+1
34
34
n+1
and A+3 corresponds to byte-1 lane of SDRAM/Hwy
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy
Byte
A+0
A+0
A+0
12
12
the first transaction is to set the SE bit in the BIU_CTL
register as described in the second paragraph of
11.6.5 on page
C.6
1. PCI Multimedia Design Guide, revision 1.0 - dated
2. Designing PCI Cards and Drivers for Power Macin-
PRELIMINARY SPECIFICATION
n
March 29,1994
tosh Computers, By Apple Computer, Inc.; Refer-
ence: R0650LL/A; Phone: [phone]
REFERENCES
Byte
A+3
A+3
A+3
12
12
11-11.
n+3
Little Endian Mode
Byte
A+2
A+2
A+2
34
34
n+2
Byte
A+1
A+1
A+1
56
56
n+1
Endian-ness
Byte
A+0
A+0
A+0
78
78
Section
n
C-9