PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 167

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
The PCI interface begins the PCI-bus transactions when
software writes to DMA_CTL. As with the I/O and config-
uration operations, the BIU_STATUS and BIU_CTL reg-
isters monitor the status of the operation and control in-
terrupt signaling.
The fully detailed description of the steps needed to start
a DMA transaction can be found in
“DMA_CTL Register.”
Image-Coprocessor DMA
The PCI interface also executes DMA transactions for
the Image Coprocessor (ICP). The ICP performs rapid
post-processing of image data and writes it at PCI DMA
speed to a PCI graphics card frame buffer. The ICP can-
not perform PCI read transactions. BIU_CTL.IE (ICP
DMA Enable) should be asserted before attempting ICP
PCI operation. Programming of ICP DMA is described in
Section 14.6, “Operation and Programming.”
11.3
The PNX1300 PCI interface responds as a target to ex-
ternal initiators for a limited set of PCI transaction types:
• Configuration read/write
• Memory read/write, read line, and read multiple to
PNX1300 ignores PCI transactions other than the above.
11.4
The PCI interface can be processing more than one op-
eration at a given time. There are five distinct classes of
operations implemented by the PCI interface:
1. DSPCPU load/store to PCI space.
2. PCI I/O read/write and PCI configuration read/write.
3. General-purpose DMA read/write.
4. ICP DMA write.
5. External-PCI-agent-initiated read/write (to PNX1300
If the active general-purpose DMA transaction is a read,
up to five transactions, one from each, can be active si-
multaneously. If the active general-purpose DMA opera-
tion is a write, then only four transactions can be active
simultaneously because general-purpose DMA writes
force ICP DMA writes to wait until the general-purpose
DMA completes. When a general-purpose DMA write is
pending, an in-progress ICP DMA operation is suspend-
ed at the next 64-byte block boundary and waits until the
completion of the DMA write operation. General-purpose
DMA reads are interleaved with ICP DMA writes, so both
can be active concurrently.
PCI single-data-phase transactions (DSPCPU load/
store, I/O read/write, and configuration read/write) are
executed in the order they are issued to the PCI inter-
face. Note the strict implementation limitation that PCI -
the PNX1300 SDRAM or MMIO apertures. See
tion 11.8, “Limitations.”
on-chip resource).
PCI INTERFACE AS A TARGET
TRANSACTION CONCURRENCY,
PRIORITIES, AND ORDERING
Section 11.6.16,
Sec-
I/O and PCI configuration transactions cannot be simul-
taneously active.
11.5
Since it is a PCI device, PNX1300 has a set of configu-
ration registers to determine PCI behavior. PCI configu-
ration registers allow full relocation of interrupt binding
and address mapping by the system’s host processor.
This relocatability of PCI-space parameters eases instal-
lation, configuration, and system boot.
The PCI standard specifies a 64-byte PCI configuration
header region within a reserved 256-byte block. During
system initialization, host system software scans the PCI
bus, looking for PCI headers, to determine what PCI de-
vices are present in the system. The fields in the header
region uniquely identify the PCI device and allow the host
to control the device in a generic way.
the layout of the configuration header region.
Figure 11-2
ration registers. Some registers, such as Device ID, have
hardwired values, while others are programmed by soft-
ware. Still others are set automatically from the external
boot ROM during PNX1300’s power-up initialization.
11.5.1
For PNX1300, the value of the 16-bit Vendor ID field is
hardwired to 0x1131 (Philips). This value identifies the
manufacturer of a PCI device. Valid vendor identifiers
are assigned by the PCI special interest group (PCI SIG)
to ensure uniqueness. The value 0xFFFF is reserved
and must be returned by the host/PCI bridge when an at-
tempt is made to read a non-existent device’s Vendor ID
configuration register.
11.5.2
For PNX1300, the value of the 16-bit Device ID field is
hardwired to 0x5402. The Device ID is assigned by the
manufacturer to uniquely identify each PCI device it
makes.
11.5.3
The 16-bit command register provides basic control over
a PCI device’s ability to generate and/or respond to PCI
bus cycles. According to the PCI specification, after re-
set, all bits in this register are cleared to ‘0’ (except for a
device that must be initially enabled). Clearing all bits to
’0’ logically disconnects the device from the PCI bus for
all accesses except configuration accesses.
The command register format is shown in
Table 11-2
values listed as ‘normally taken’ are not necessarily the
reset values, i.e. the Command register is reset to all ‘0’s,
meaning the features are disconnected on reset.
Following are detailed descriptions of the command reg-
ister fields.
PRELIMINARY SPECIFICATION
REGISTERS ADDRESSED IN PCI
CONFIGURATION SPACE
Vendor ID Register
Device ID Register
Command Register
summarizes the field values. Note that the
also shows the initial values for the configu-
Figure 11-2
PCI Interface
Figure
shows
11-3.
11-3