PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 406

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Signed 8-bit load
pseudo-op for ild8d(0)
SYNTAX
FUNCTION
DESCRIPTION
argument. (Note: pseudo operations cannot be used in assembly source files.)
and stores the result in rdest. This operation does not depend on the bytesex bit in the PCSW since only a single byte
is loaded.
defined only for 32-bit loads and stores.
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed location is cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
r10 = 0xd00, [0xd00] = 0x22
r30 = 0, r20 = 0xd04, [0xd04] = 0x84
r40 = 1, r20 = 0xd04, [0xd04] = 0x84
r50 = 0xd01, [0xd01] = 0x33
The
The
The result of an access by
The
[ IF rguard ] ild8 rsrc1 → rdest
if rguard then
rdest ← sign_ext8to32(mem[rsrc1])
ild8
ild8
ild8
Initial Values
operation loads the 8-bit memory value from the address contained in rsrc1, sign extends it to 32 bits,
ild8
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation is a pseudo operation transformed by the scheduler into an
has no side effects whatever.
ild8
ild8 r10 → r60
IF r30 ild8 r20 → r70
IF r40 ild8 r20 → r80
ild8 r50 → r90
to the MMIO address aperture is undefined; access to the MMIO aperture is
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r60 ← 0x00000022
no change, since guard is false
r80 ← 0xffffff84
r90 ← 0x00000033
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
uld8 ild8d uld8d ild8r
ild8d(0)
ATTRIBUTES
SEE ALSO
Result
uld8r
with the same
dmem
192
4, 5
ild8
No
—
1
3
A-108