PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 103

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
pixel end up in adjacent memory locations. Note that
blanking information capture only makes sense in fullres
mode with co-sited sampling. All other modes apply filter-
ing, which will distort the numeric sample values.
The captured image is stored in SDRAM at a location de-
fined by the storage parameters in MMIO registers
(Y_BASE_ADR, Y_DELTA, U_BASE_ADR, U_DELTA,
V_BASE_ADR, V_DELTA). Note that the base-address
registers force alignment to 64-byte boundaries (six
LSBs are always zero). The default memory packing is
big-endian although little-endian packing is also support-
ed by setting the LITTLE_ENDIAN bit in the VI_CTL reg-
ister.
• Y_BASE_ADR: The desired starting (byte) address
• Y_DELTA: The desired address difference between
Figure 6-10. VI YUV 4:2:2 planar memory format.
Modifications to Y_BASE_ADR, U_BASE_ADR and
V_BASE_ADR have no effect until the start of next cap-
ture, i.e. VI hardware maintains a separate pointer to
track the current address. Modifications to Y_DELTA,
U_DELTA and V_DELTA do affect the next horizontal re-
trace. Hence, under normal circumstances, the DELTA
variables should not be changed during capture.
When capture is complete, i.e. any internal VI buffers
have been flushed and the entire captured image is in lo-
cal SDRAM, VI raises the STATUS register flag CAP-
TURE COMPLETE. If enabled in the VI_CTL register,
this event causes a DSPCPU interrupt to be requested.
The programmer can determine whether the captured
image is a field1 or field2 by inspection of the FIELD2 flag
in VI_STATUS. Note that the FIELD2 flag changes at the
start of the vertical blanking interval of the next field.
in SDRAM memory where the first Y (luminance)
sample of the captured image will be stored. This
address is forced to be 64-byte aligned (six LSBs
always ‘0’).
the last sample of a line and the address of the first
sample on the next line. Note that the value of
Y_BASE_ADR
U_BASE_ADR
Y_DELTA
U_DELTA
pix0
pix0
WIDTH/2 pixels
pix1
pix2
pix2
•
•
WIDTH pixels
•
• U_BASE_ADR,
Horizontally-adjacent samples are stored at successive
byte addresses, resulting in a packed form (four 8-bit
samples are packed into one 32-bit word). Upon horizon-
tal retrace, pixel storage addresses are incremented by
the corresponding DELTA to compute the starting byte
address for the next line. Note that DELTA is a 16-bit un-
signed quantity. This process continues until HEIGHT
lines of WIDTH samples have been stored in memory for
luminance (Y). For chrominance, HEIGHT lines of half
the WIDTH are stored
The CAPTURE COMPLETE flag is cleared by writing a
word to VI_CTL with a ‘1’ in the CAPTURE COMPLETE
ACK bit position. This action has the following effect:
• it tells the hardware that a new Y,U, and V DMA
• it clears the CAPTURE COMPLETE flag
• it tells VI to capture the next image
The user can program the Y_THRESHOLD field to gen-
erate pre-completion (or post-completion) interrupts.
Whenever
THRESHOLD REACHED flag in the STATUS register is
set. If enabled in the VI_CTL register, this event causes
a DSPCPU interrupt request. The THRESHOLD
REACHED flag is cleared by writing a word to VI_CTL
with a ‘1’ in the THRESHOLD REACHED ACK bit posi-
tion. Note that, due to internal buffering in the VI unit, it is
NOT guaranteed that all samples from lines up to and in-
PRELIMINARY SPECIFICATION
•
1.
Y_DELTA must be chosen so that all line-start
addresses are 64-byte aligned.
V_DELTA: Same functions and alignment restric-
tions as above, but for chrominance-component
samples.
buffer is available (or the old one has been copied)
•
Note that consecutive pixel components of each line
are stored in consecutive memory addresses but con-
secutive lines need not be in consecutive memory ad-
dresses
•
(Repeated for V_BASE_ADDR,
CUR_Y
W–1
pix
V_DELTA)
1
reaches
. See
U_DELTA,
Figure
Y_THRESHOLD,
6-10.
V_BASE_ADR,
Video In
6-7
the