PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 356

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Sign of floating-point value
SYNTAX
FUNCTION
DESCRIPTION
in rsrc1. rdest is set to 0 if rsrc1 is equal to zero, to 1 if rsrc1 is positive, or to –1 if rsrc1 is negative. The argument is
treated as an IEEE single-precision floating-point value; the result is an integer. If the argument is denormalized, zero
is substituted before computing the comparison, and the IFZ flag in the PCSW is set; thus, the result of
denormalized argument is 0. If
are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation but
can only be reset by an explicit
time as rdest is written. If any other floating-point compute operations update the PCSW at the same time, the net
result in each exception flag is the logical OR of all simultaneous updates ORed with the existing PCSW value for that
exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0)
r40 = 0xbf800000 (-1.0)
r50 = 0x80800000 (-1.175494351e-38)
r60 = 0x80400000 (-5.877471754e-39)
r10 = 0, r70 = 0xffffffff (QNaN)
r20 = 1, r70 = 0xffffffff (QNaN)
r80 = 0xff800000 (-INF)
The
The
The
[ IF rguard ] fsign rsrc1 → rdest
if rguard then {
}
if (float)rsrc1 = 0.0 then
else if (float)rsrc1 < 0.0 then
else
fsign
fsignflags
fsign
rdest ← 0
rdest ← 0xffffffff
rdest ← 1
Initial Values
operation sets the destination register, rdest, to either 0, 1, or –1 depending on the sign of the argument
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the exception flags that would result from an individual
writepcsw
fsign
fsign r30 → r100
fsign r40 → r105
fsign r50 → r110
fsign r60 → r115
IF r10 fsign r70 → r116
IF r20 fsign r70 → r117
fsign r80 → r120
causes an IEEE exception, the corresponding exception flags in the PCSW
operation. The update of the PCSW exception flags occurs at the same
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r100 ← 1
r105 ← 0xffffffff (-1)
r110 ← 0xffffffff (-1)
r115 ← 0, IFZ flag set
no change, since guard is false
r117 ← 0, INV flag set
r120 ← 0xffffffff (-1)
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
fsignflags readpcsw
ATTRIBUTES
writepcsw
SEE ALSO
Result
fsign
fsign
.
fsign
fcomp
152
No
—
1
1
3
A-58
for a