PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 461

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
st16d
SYNTAX
FUNCTION
DESCRIPTION
arguments. (Note: pseudo operations cannot be used in assembly files.)
address in rsrc1 + d. The d value is an opcode modifier, must be in the range –128 and 126 inclusive, and must be a
multiple of 2. This store operation is performed as little-endian or big-endian depending on the current setting of the
bytesex bit in the PCSW.
undefined, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE
(TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next
interruptible jump.
defined only for 32-bit loads and stores.
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st16d has no side effects whatever; in particular,
the LRU and other status bits in the data cache are not affected.
EXAMPLES
A-163
r10 = 0xcfe, r80 = 0x44332211
r50 = 0, r20 = 0xd05,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd06,
r70 = 0xaabbccdd
The
The
If
The result of an access by
The
[ IF rguard ] st16d(d) rsrc1 rsrc2
if rguard then {
}
st16d
if PCSW.bytesex = LITTLE_ENDIAN then
else
mem[rsrc1 + d + (1 ⊕ bs)] ← rsrc2<7:0>
mem[rsrc1 + d + (0 ⊕ bs)] ← rsrc2<15:8>
st16d
st16d
bs ← 1
bs ← 0
st16d
Initial Values
is misaligned (the memory address computed by rsrc1 + d is not a multiple of 2), the result of
operation stores the least-significant 16-bit halfword of rsrc2 into the memory locations pointed to by the
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation is a pseudo operation transformed by the scheduler into an
PRELIMINARY SPECIFICATION
st16d
st16d(2) r10 r80
IF r50 st16d(–4) r20 r70
IF r60 st16d(–4) r30 r70
to the MMIO address aperture is undefined; access to the MMIO aperture is
Operation
16-bit store with displacement
[0xd00] ← 0x22, [0xd01] ← 0x11
no change, since guard is false
[0xd02] ← 0xcc, [0xd03] ← 0xdd
st16 h_st16d st8 st8d st32
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
Philips Semiconductors
pseudo-op for h_st16d
h_st16d
ATTRIBUTES
SEE ALSO
Result
st32d
with the same
–128..126 by 2
dmem
7 bits
st16d
4, 5
n/a
30
2
is