PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 165

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PCI Interface
11.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 includes a PCI interface for easy integration
into personal computer applications—where the PCI-bus
is the standard for high-speed peripherals. In embedded
applications, with PNX1300 serving as the main CPU,
the PCI bus can interface to peripheral devices that im-
plement functions not provided by the on-chip peripher-
als. See
The main function of the PCI interface is to connect the
PNX1300 on-chip highway and PCI buses. A bus cycle
on the internal highway that targets an address mapped
into PCI space will cause the PCI interface to create a
PCI bus cycle. Similarly, a bus cycle on PCI that targets
an address mapped into PNX1300 memory space will
cause the PCI interface to create a highway bus cycle
targeted at SDRAM. For some operations, the PCI inter-
face is explicitly programmed by the DSPCPU.
From PNX1300, only the DSPCPU and the image copro-
cessor (ICP) unit can cause the PCI interface to create
PCI bus cycles; the other on-chip peripherals cannot see
external hardware through the PCI interface. From PCI,
SDRAM and most of the registers in MMIO space can be
accessed by external PCI initiators.
The PCI interface implements DMA (also called block or
burst) and non-DMA transfers. DMA transfers are inter-
ruptible on 64-byte boundaries. The PCI interface can
service outbound (PNX1300 → PCI) and inbound (PCI
→ PNX1300) data flows simultaneously.
Table 11-1
Figure 11-1. Two typical system implementations: (a) shows PNX1300 as a PCI peripheral in a desktop PC, (b)
shows an embedded system with PNX1300 as the host CPU.
PCI Agent
PCI OVERVIEW
PNX1300
Figure
lists some of the features of the PCI interface.
11-1.
PCI Bus
a) PNX1300 as peripheral
Controller
Interrupt
PCI Agent
PCI Bridge
PCI Bus
Arbiter
Host CPU
(e.g., x86)
PCI Agent
by Gert Slavenburg, Ken-Sue Tan, Babu Kandimalla
Table 11-1. PCI interface characteristics
PNX1300 DMA read transactions use an efficient ‘mem-
ory read multiple’ PCI transactions, unless explicitly dis-
abled.
PNX1300 contains an on-board PCI_CLK generator for
low-cost configurations. It can be enabled/disabled at
boot time. See
PNX1300 has a sideband control signal that allows glue-
less connection of simple slave peripherals directly to the
PCI bus wires. This can be used to connect Flash, ROM,
SRAM, UARTs, etc. with 8-bit data and demultiplexed
addresses. Refer to
Bus.”
PRELIMINARY SPECIFICATION
PCI Compliance
PCI Speed
Data bus width
Address space
Voltage levels
Burst mode
Posted write
PCI ‘special cycle’
PCI ‘memory write &
invalidate’
PCI ‘interrupt acknowl-
edge’
PCI ‘dual-address
cycle’
PCI Agent
Characteristic
PNX1300
Section
PCI Bus
11.6.5.
Section 13.1 on page
b) PNX1300 as host CPU
PCI Bus
Arbiter
Chapter 22, “PCI-XIO External I/O
PCI Agent
PCI Local Bus Specification Rev. 2.1
Up to 33 MHz
32-bit only
32 bits (4 GB)
Drive & receive at either 3.3 V or 5V
Yes, w/ double buffering so maxi-
mum transfer rate (132 MB/sec) is
sustainable
Yes, can be disabled
Not recognized
Supported for PNX1300 as initiator
Not generated
Not generated
Chapter 11
Comments
13-1.
PCI Agent
11-1