PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 287

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
chip enable. If more than one device is to be added, an
external decoder, such as a 74FCT138, can be used to
decode the upper bits of the 24-bit transfer address, with
the PCI_INTB# line used as a global chip enable to the
decoder.
The PCI-XIO Bus controller has a wait state generator to
provide timing for slow devices. The wait state generator
allows the addition of up to 7 wait states for slow chip ac-
cess and write times. The wait state generator logic gen-
erates the PCI_TRDY# signal to the PCI bus.
The XIO Bus controller contains a clock generator for
standalone systems. The PCI-XIO Bus uses the PCI
clock. This clock is normally supplied by a PCI Bus cen-
tral resource outside the PNX1300 chip. In standalone or
low-cost systems, the internal clock generator can be
used. The internal clock generator divides the PNX1300
highway clock by a 5-bit number in a prescaler. This al-
lows setting bus clocks from 4 MHz to 66 MHz in a 133
MHz system. The internal clock generator programming
is described in
Figure 22-2. PCI-XIO bus device CONCEPTUAL block diagram
Section 22.5, “XIO_CTL MMIO Register.”
Unit (BIU)
PCI
Bus
Interface
XIO Bus
Controller
PCI Device
PNX1300
PCI Bus
XIO Bus
22.2
Figure 22-2
PCI-XIO Bus as a slave device on the PCI Bus. The XIO
Bus Controller generates an XIO Bus, which is an 8-bit
bus with a 24-bit address. Devices attached to the XIO
Bus appear as memory locations in the 16 MB address
space of the XIO Bus.
Figure 22-3
the PCI_XIO Bus. To conserve pins, the XIO Bus Con-
troller uses the PCI I/O pins as XIO Bus pins during XIO
Bus data transfers. It reconfigures the 32 PCI address/
data pins as 8 XIO Bus data pins and 24 XIO Bus ad-
dress pins, and it reconfigures the byte enable pins as
XIO Bus timing signals. By changing the functions of the
pins during the transfer, 36 pins are saved which would
otherwise be required to drive the XIO Bus devices. By
reconfiguring the PCI pins only during the data phase of
the XIO Bus transfers, the PCI-XIO bus retains its PCI
Bus compatibility.
Figure 22-4
PCI-XIO Bus controller.
PRELIMINARY SPECIFICATION
for address & data, these use the same pins/wires
8-bit data + 24-bit addresses
BLOCK DIAGRAM
PCI
Device
shows a more detailed block diagram of the
shows an implementation block diagram of
shows a conceptual block diagram of the
x86
Device
PCI
Device
PCI-XIO External I/O Bus
ROM
PCI
Host
22-3