PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 66

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Programmer’s note: See the Philips TriMedia Cookbook
(Book 2 of TriMedia SDE documentation) for information
on writing interrupt handlers.
3.5.3.2
DSPCPU interrupt sources can be programmed to oper-
ate in either level-sensitive or edge-triggered mode. Op-
eration in edge-triggered or level-sensitive mode is de-
termined by a bit in the ISETTING MMIO locations
corresponding to the source, as defined in
On RESET, all ISETTING registers are cleared.
In edge-triggered mode, the leading edge of the signal
on the device interrupt request line causes the VIC (Vec-
tored Interrupt Controller) to set the interrupt pending flag
corresponding to the device source number. Note that,
for active high signals, the leading edge is the positive
edge, whereas for active low request signals (such as
PCI INTA#), the negative edge is the leading edge. The
interrupt remains pending until one of two events occurs:
• The VIC successfully dispatches the vector corre-
• PNX1300 CPU software clears the interrupt-pending
No interrupt acknowledge to ICLEAR is needed for de-
vices operating in edge-triggered mode, since the vector
dispatch clears the IPENDING request. The device itself
may however need a device-specific interrupt acknowl-
edge to clear the requesting condition. Edge-triggered
mode is not recommended for devices that can signal
multiple simultaneous interrupt conditions. The on-chip
timers must be operated in edge triggered mode.
In level-sensitive mode, the device requests an interrupt
by asserting the VIC source request line. The device
holds the request until the device interrupt handler per-
forms a device interrupt acknowledge. It is highly recom-
mended that all off-chip and on-chip sources, with the ex-
ception of the timers, operate in level-sensitive mode.
3.5.3.3
All devices capable of generating level-triggered inter-
rupts have interrupt acknowledge bits in their memory
mapped control registers for this purpose. An interrupt
acknowledge is performed by a store to such control reg-
Figure 3-7. Interrupt mode and priority MMIO locations and formats.
3-10
sponding to the source to the PNX1300 CPU, or
flag by a direct write to the ICLEAR location.
MMIO_BASE
0x10 081C
0x10 0818
0x10 0814
0x10 0810
offset:
Interrupt modes
Device interrupt acknowledge
ISETTING3 (r/w)
ISETTING2 (r/w)
ISETTING1 (r/w)
ISETTING0 (r/w)
PRELIMINARY SPECIFICATION
Each MP Field:
0xxx
1xxx
31
source operates in edge-triggered mode
source operates in level-sensitive mode
MP31
MP23
MP15
MP7
Figure
27
MP30
MP22
MP14
MP6
3-7.
23
MP29
MP21
MP13
MP5
ister, with a ‘1’ in the bit position(s) corresponding to the
desired acknowledge flags.
Programmers note: the store operation that performs the
interrupt acknowledge should be issued at least 2 cycles
before the (interruptible) jump that ends an interrupt han-
dler. This ensures that the same interrupt is not dis-
patched twice due to request de-assertion clock delays.
3.5.3.4
Each interrupt source can be programmed to request
one out of eight levels of priorities. The highest priority
level (level 7) corresponds to requesting an NMI—an in-
terrupt that cannot be masked by the DSPCPU PC-
SW.IEN bit. The other levels request regular interrupts,
that can be masked as a group by the PCSW.IEN flag.
Level six represents the highest priority normal interrupt
level and level zero represents the lowest. Refer to
Figure 3-7
The VIC arbitrates the highest-priority pending interrupt
requestor. Sources programmed to request at the same
level are treated with a fixed priority, from source number
0 (highest) to 31 (lowest). At such time as the DSPCPU
is willing to process special events, the vector of highest
priority NMI source will be dispatched. If no NMI is pend-
ing, and the DSPCPU allows regular interrupts (PC-
SW.IEN is asserted), the vector of the highest priority
regular source is dispatched. Once a vector is dis-
patched, the corresponding interrupt pending flag is de-
asserted (edge triggered mode sources only).
3.5.3.5
A single MMIO register (IMASK in
masking of an arbitrary subset of the interrupt sources.
Masking applies to both regular as well as NMI level re-
questors. Masking is used by software to disable unused
devices and/or to implement nested interrupt handling. In
the latter case, each interrupt handler can stack the old
IMASK content for later restoration and insert a new
mask that only allows the interrupts it is willing to handle.
For level-triggered device handlers, IMASK should also
exclude the device itself to prevent repeated handler ac-
tivation.
Each interrupt source device typically has its own inter-
rupt enable flag(s) that determine whether certain key
19
MP28
MP20
MP12
MP4
for details of programming the priority level.
Interrupt priorities
Interrupt masking
15
MP27
MP19
MP11
MP3
Each MP Field:
x111
x110
x000
11
...
MP26
MP18
MP10
MP2
Philips Semiconductors
NMI (highest) priority
maskable level 6
maskable level 0
7
MP25
MP17
MP9
MP1
Figure
3
3-8) allows
MP24
MP16
MP8
MP0
0