PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 478

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
IEEE status flags from convert unsigned integer
to floating-point
SYNTAX
FUNCTION
DESCRIPTION
integer in rsrc1 to a single-precision IEEE floating-point value, and an integer bit vector representing the computed
exception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits in
the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is according to the IEEE
rounding mode bits in PCSW.
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
r30 = 3
r40 = 0xffffffff (4294967295)
r10 = 0, r50 = 0xfffffffd
r20 = 1, r50 = 0xfffffffd
r60 = 0x7fffffff (2147483647)
r70 = 0x80000000 (2147483648)
r80 = 0x7ffffff1 (2147483633)
The
The
[ IF rguard ] ufloatflags rsrc1 → rdest
if rguard then
rdest ← ieee_flags((float) ((unsigned long)rsrc1))
ufloatflags
ufloatflags
31
0
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls
operation computes the IEEE exceptions that would result from converting the unsigned
ufloatflags r30 → r100
ufloatflags r40 → r105
IF r10 ufloatflags r50 → r110
IF r20 ufloatflags r50 → r115
ufloatflags r60 → r117
ufloatflags r70 → r120
ufloatflags r80 → r122
Operation
PRELIMINARY SPECIFICATION
7
0
OFZ
6
PNX1300/01/02/11 DSPCPU Operations
IFZ
5
INV
r100 ← 0
r105 ← 0x02 (INX)
no change, since guard is false
r115 ← 0x02 (INX)
r117 ← 0x02 (INX)
r120 ← 0
r122 ← 0x02 (INX)
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
OVF
3
ufloat ifloatflags
ifloatrzflags
ufloatrzflags
UNF
ATTRIBUTES
2
SEE ALSO
ufloatflags
Result
INX
1
DBZ
0
falu
128
1, 4
No
—
1
3
A-180