PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 57

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

DSPCPU Architecture
3.1
In the document the generic PNX1300 product name
refers to PNX1300 Series, or the PNX1300/01/02/11
products.
This section documents the system programmer or
‘bare-machine’ view of the PNX1300 CPU (or DSPCPU).
3.1.1
Figure 3-1
registers, r0...r127. In addition to the hardware program
counter, PC, there are 4 user-accessible special purpose
registers, PCSW, DPC (destination program counter),
SPC (source program counter), and CCCOUNT.
Table 3-1
Register r0 always contains the integer value '0', corre-
sponding to the boolean value 'FALSE' or the single-pre-
cision floating point value +0.0. Register r1 always con-
tains the integer value '1' ('TRUE'). The programmer is
NOT allowed to write to r0 or r1.
Registers r2 through r127 are true general purpose reg-
isters; the hardware does not imply their use in any way,
Figure 3-1. PNX1300 registers.
Note: Writing to r0 or r1 may cause reads from r0 or
r1 scheduled in adjacent clock cycles to return unpre-
dictable values. The standard assembler prevents/
forbids the use of r0 or r1 as a destination register.
63
128 General-Purpose Registers
System Status & Control Registers
BASIC ARCHITECTURE CONCEPTS
• r0 & r1 fixed
• r2–r127 variable
Register Model
lists the registers and their purposes.
shows the DSPCPU’s 128 general purpose
55
47
39
31
31
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
though compiler or programmer conventions may assign
particular roles to particular registers. The DPC and SPC
relate to interrupt and exception handling and are treated
in
tion Program Counter.”
and Status Word) register is treated in
“PCSW Overview.”
counter is treated in
Cycle Counter.”
Table 3-1. DSPCPU registers
PRELIMINARY SPECIFICATION
CCCOUNT 64 bits Counts clock cycles since reset
Register
Section 3.1.4, “SPC and DPC—Source and Destina-
r2–r127
PCSW
DPC
SPC
PC
23
23
r0
r1
by Gert Slavenburg, Marcel Janssens
32 bits Always reads as 0x0; must not be used
32 bits Always reads as 0x1; must not be used
32 bits 126 general-purpose registers
32 bits Program counter
32 bits Program control & status word
32 bits Destination program counter; latches
32 bits Source program counter; latches tar-
Size
15
15
•
•
•
as destination of operations
as destination of operations
target of taken branch that is interrupted
get of taken branch that is not inter-
rupted
CCCOUNT, the 64-bit clock cycle
Section 3.1.5, “CCCOUNT—Clock
The PCSW (Program Control
7
7
Chapter 3
Details
0
0
0
1
0
0
Section 3.1.3,
r0
r1
r2
r3
r126
r127
PC
PCSW
DPC
SPC
CCCOUNT
•
•
•
3-1