PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 358

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Floating-point square root
SYNTAX
FUNCTION
DESCRIPTION
single-precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument
is denormalized, zero is substituted for the argument before computing the squareroot, and the IFZ flag in the PCSW
is set. If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
causes an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are
sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r60 = 0xc0400000 (–3.0)
r40 = 0x40400000 (3.0)
r10 = 0, r40 = 0x40400000 (3.0)
r20 = 1, r40 = 0x40400000 (3.0)
r82 = 0x00c00000 (1.763241526e–38)
r84 = 0x7f800000 (+INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00400000 (5.877471754e-39)
The
The
The
[ IF rguard ] fsqrt rsrc1 → rdest
if rguard then
fsqrtflags
fsqrt
fsqrt
rdest ← square_root(rsrc1)
Initial Values
operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any
operation computes the squareroot of rsrc1 and stores the result into rdest. All values are in IEEE
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the exception flags that would result from an individual
fsqrt r60 → r90
fsqrt r40 → r95
IF r10 fsqrt r40 → r100
IF r20 fsqrt r40 → r110
fsqrt r82 → r112
fsqrt r84 → r113
fsqrt r70 → r120
fsqrt r80 → r125
Operation
PRELIMINARY SPECIFICATION
r90 ← 0xffffffff (QNaN), INV flag set
r95 ← 0x3fddb3d7 (1.732051), INX flag set
no change, since guard is false
r110 ← 0x3fddb3d7 (1.732051), INX flag set
r112 ← 0x201cc471 (1.32787105e-19), INX flag set
r113 ← 0x7f800000 (+INF)
r120 ← 0x5f7fffff (1.8446743e19), INX flag set
r125 ← 0, IFZ flag set
PNX1300/01/02/11 DSPCPU Operations
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Recovery
Issue slots
fsqrtflags readpcsw
Result
ATTRIBUTES
writepcsw
SEE ALSO
fsqrt
.
fsqrt
ftough
110
No
fsqrt
16
—
17
1
2
A-60