PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 58

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
3.1.2
The DSPCPU issues one ‘long instruction’ every clock
cycle. Each instruction consists of several operations
(five operations for the PNX1300 microprocessor). Each
operation is comparable to a RISC machine instruction,
except that the execution of an operation is conditional
upon the content of a general purpose register. Exam-
ples of operations are:
Each operation has a specific, known execution latency
in clock cycles. For example, iadd takes 1 cycle; thus the
result of an iadd operation started in clock cycle i is avail-
able for use as an argument to operations issued in cycle
i+1 or later. The other operations issued in cycle i cannot
use the result of iadd. The ld32d operation has a latency
of 3 cycles. The result of an ld32d operation started in cy-
cle j is available for use by other operations issued in cy-
cle j+3 or later. Branches, such as the jmpf example
above have three delay slots. This means that if a branch
operation in cycle k is taken, all operations in the instruc-
tions in cycle k+1, k+2 and k+3 are still executed.
In the above examples, r10 and r20 control conditional
execution of the operations. Also known as ‘guarding’,
here r10 and r20 contain the operation ‘guard’. See
tion 3.2.1, “Guarding (Conditional Execution).”
Certain restrictions exist in the choice of what operations
can be packed into an instruction. For example, the
DSPCPU in PNX1300 allows no more than two load/
store class operations to be packed into a single instruc-
tion. Also, no more than five results (of previously started
operations) can be written during any one cycle. The
packing of operations is not normally done by the pro-
grammer. Instead, the instruction scheduler (See Philips
TriMedia SDE Reference Manual) takes care of convert-
ing the parallel intermediate format code into packed in-
structions ready for the assembler. The rules are formally
described in the machine description file used by the in-
struction scheduler and other tools.
Figure 3-2. PNX1300 PCSW (Program Control and Status Word) register format.
3-2
exception trap enable
Misaligned store exception
PCSW[31:16]
Write back error trap enable
PCSW[15:0]
IF r10 iadd r11 r12 → r13
IF r10 ld32d(4) r15 → r16
IF r20 jmpf r21 r22
Misaligned store
Reserved exception
(if r10 true, add r11 and r12 and write sum in r13)
(if r10 true, load 32 bits from mem[r15+4] into r16)
(if r20 true and r21 false, jump to address in r22)
Write back error
Basic DSPCPU Execution Model
MSE
MSE
TRP
15
31
Interrupt enable (1 ⇒ allow interrupts)
PRELIMINARY SPECIFICATION
WBE RSE
WBE
TRP
14
30
Count stalls (1 ⇒ Yes)
Reserved exception
trap enable
TRP
RSE
29
13
U N D E F
12
28
U N D E F
CS
11
27
TFE
IEN
10
26
Sec-
Trap on first exit
BSX IEEE MODE OFZ
25
9
U N D E F I N E D
Byte sex (1 ⇒ little endian)
3.1.3
Figure 3-2
ue of PCSW on reset is 0x800. For compatibility, any un-
defined PCSW fields should never be modified.
Note that the DSPCPU architecture has no condition
codes or integer arithmetic status flags. Integer opera-
tions that generate out-of-range results deliver an opera-
tion specific bit pattern. For examples, see
Appendix A, “PNX1300/01/02/11 DSPCPU Operations.”
Predicate operations exist that take the place of integer
status flags in a classical architecture. Multiword arith-
metic is supported by the ‘carry’ operation which gener-
ates a ‘0’ or ‘1’ depending on the carry that would be gen-
erated if its arguments were summed.
FP-Related Fields.The IEEE mode field determines the
IEEE rounding mode of all floating point operations, with
the exception of a few floating point conversion opera-
tions that use fixed rounding mode. For examples, see
ixrz, ifloatrz, ifixrz,
02/11 DSPCPU Operations.”
The FP exception flags are ‘sticky bits’ that are set as a
side effect of floating-point computations. Each floating
point operation can set one or more of the flags if it incurs
the corresponding exception. The flags can only be reset
by direct software manipulation of the PCSW (using the
writepcsw operation). The bits have the meanings shown
in
The FP exception trap enable bits determine which FP
exception flags invoke CPU exception handling. An ex-
ception is requested if the intersection of the exception
flags and trap enable flags is non-zero. The acceptance
and handling of exceptions is described in
“Special Event Handling.”
BSX (Bytesex). The DSPCPU has a switchable bytesex.
The BSX flag in the PCSW can be written by software.
Load/store operations observe little- or big-endian byte
ordering based on the current setting of BSX.
IEN (Interrupt Enable). The IEN flag disables or enables
interrupt processing for most interrupt sources. Only NMI
(non-maskable interrupt) bypasses IEN. The acceptance
and handling of interrupts is described in
“INT and NMI (Maskable and Non-Maskable Interrupts).”
8
Table
IEEE rounding mode
0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
23
7
3-2.
PCSW Overview
shows the PCSW register. The PNX1300 val-
TRP
OFZ
22
6
TRP
IFZ
IFZ
ifloatrz
21
5
FP exception trap-enable bits
TRP
INV
INV
20
4
in
Philips Semiconductors
FP exceptions
Appendix A, “PNX1300/01/
PCSW = 0x800
after RESET
OVF
OVF
TRP
19
3
UNF
TRP
UNF
18
2
Section 3.5.3,
TRP
INX
INX
Section 3.5,
17
1
dspiadd
DBZ
TRP
DBZ
16
0
if-
in