PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 172

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Hardware RESET initializes DRAM_BASE to 0x0 and
MMIO_BASE to 0xefe0,0000, after which the PNX1300
boot protocol sets the final value.
In standalone systems, the autonomous boot sequence
is executed. In this case, the values of DRAM_BASE and
MMIO_BASE are copied from the content of the serial
boot EEPROM, as described in
DSPCPU Program Load for Autonomous Bootstrap.”
In X86 or other host-assisted platforms, the PCI host as-
sisted boot sequence is executed. In this case, the base
registers are not set from the EEPROM. Instead, the host
BIOS executes a scan for devices on each PCI bus. Dur-
ing this scan, memory apertures needed by each device
are determined, and a suitable base is assigned by the
host BIOS. The details of this process are described be-
low.
Figure 11-7
MMIO_BASE. Following are descriptions of the register
fields.
M (Memory). The value of the M bit indicates whether
the desired resource is a memory or PC I/O aperture.
The M bit is hardwired to ’0’, indicating a memory type
aperture for both the DRAM_BASE and MMIO_BASE
registers.
T (Type). The value of the T field indicates the size of the
base address register and constraints on its relocatabili-
ty.
T field.
Table 11-10. Type field encodings
PNX1300’s PCI-interface base registers are 32 bits wide
and can be relocated in the 32-bit address space; thus,
the value of the T field is ‘00’ for both DRAM_BASE and
MMIO_BASE.
P (Prefetchable). The value of the P bit indicates to oth-
er devices whether or not the range is prefetchable.
Figure 11-7. Base address register format.
11-8
Type
Table 11-10
00
01
10
11
Base register is 32 bits wide; mapping can relocate
anywhere in 32-bit memory space
Base register is 32 bits wide; mapping must relocate
below 1 MB in memory space
Base register is 64 bits wide; mapping can relocate
anywhere in 64-bit address space
Reserved
DRAM_BASE
MMIO_BASE
shows the formats for DRAM_BASE and
lists the encodings and meanings of the
PRELIMINARY SPECIFICATION
31
31
Meaning
Section 13.2.2, “Initial
sp
25
sp
sp
sp
sp
DRAM Base Address
MMIO Base Address
sp
20
0
19
0
0
0
0
0
0
0
0
The P bit in DRAM_BASE reflects the DRAM prefetch-
able attribute as set by the prefetchable bit in the boot
prom (Refer to
ming).
MMIO is not prefetchable, so the P bit is hardwired to ’0’
for MMIO_BASE.
Being prefetchable means there are no side effects on
reads, the device returns all bytes on reads regardless of
the byte enables, and host bridges can merge processor
writes into this range without causing errors.
Note: the setting of the P bit does not change the behav-
ior of the cache or memory interface. It simply signals the
host if the range is assumed to be prefetchable.
DRAM/MMIO base address. In X86 or other host plat-
forms, the configuration space DRAM Base Address and
MMIO Base Address fields serve two purposes. First, the
host BIOS software can use them to determine the sizes
of the SDRAM and MMIO apertures. Second, the BIOS
can write to these fields to cause the apertures to be re-
located within the PCI memory address space.
To determine the sizes of an aperture, the BIOS first
writes all ‘1’s (0xFFFFFFFF) to the address field. When
the BIOS reads the field immediately after, the value re-
turned will have ’0’s in all don’t-care bits and ‘1’s in all re-
quired address bits. Required address bits form a left-
aligned (i.e., starting at the MSB) contiguous field of ‘1’s,
thus effectively specifying the size of the aperture.
For example, the MMIO aperture is a fixed 2-MB space.
After writing all ‘1’s to the MMIO Base Address field, a
subsequent read returns the value 0xFFE00000. The M,
T, and P fields are all ’0’ indicating the aperture is mem-
ory (not I/O), can be relocated anywhere in a 32-bit ad-
dress space, and is not prefetchable. Since the aperture
has 21 address bits (the position of the first ’1’ bit), MMIO
space is a 2-MB aperture (2
assigns a suitable 2-MB aligned base address by writing
to the MMIO_BASE register in configuration space.
The DRAM aperture can range in size from 1 MB to 64
MB (but the size must be a power of 2). Thus, the number
of required address bits can range from 20 to 26. The ac-
tual amount of SDRAM present is determined by the con-
tent of the first byte of the boot EEPROM, as described
in
BIU uses this size to determine which of the bits marked
‘sp’ in
This causes the BIOS to determine the correct actual
DRAM aperture size.
0
0
Section 13.4, “Detailed EEPROM Contents.”
0
0
Figure 11-7
0
0
0
0
0
0
0
0
Table 13-5 on page 13-7
0
0
0
0
are writable and which are set to ‘0’.
0
0
0
0
0
0
Philips Semiconductors
21
4
0
4
0
bytes). The host BIOS now
P
P
3
3
2
2
T
T
1
1
M
M
0
0
for program-
The PCI