PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 107

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
and SIZE (in number of samples), it is safe to enable cap-
ture by setting CAPTURE_ENABLE. Note that SIZE is in
samples and must be a multiple of 64, hence setting a
minimum buffer size of 64 bytes for raw8 mode and 128
bytes for raw10 modes. At this point, buffer1 is the active
capture buffer. Data is captured in buffer1 until capture is
disabled or until SIZE samples have been captured. After
every sample, a running address pointer is incremented
by the sample size (one or two bytes). If SIZE samples
have been captured, capture continues (without missing
a sample) in buffer2. At the same time, BUF1FULL is as-
serted. This causes an interrupt on the DSPCPU, if en-
abled by BUF1FULL INTERRUPT ENABLE.
Buffer2 is now the active capture buffer and behaves as
described above. In normal operation, the DSPCPU will
respond to the BUF1FULL event by assigning a new
BASE1 and (optionally) SIZE and performing an ACK1.
If the DSPCPU fails to assign a new buffer1 and per-
forms an ACK1 before buffer2 also fills up, the OVER-
RUN condition is raised and capture stops. Capture con-
tinues upon receipt of an ACK1, ACK2, or both,
regardless of the OVERRUN state. The buffer in which
capture resumes is as indicated in
OVERRUN condition is ‘sticky’ and can only be cleared
by software, by writing a ‘1’ to the ACK_OVR bit in the
VI_CTL register.
If insufficient bandwidth is allocated from the internal
data highway, the VI internal buffers may overflow. This
Figure 6-16. VI raw mode major states.
1.
SDRAM buffers must start on a 64-byte boundary.
RESET
ACK2
Figure
6-16. The
ACTIVE = BUF1
ACTIVE = BUF2
ACTIVE = BUF2
ACTIVE = BUF1
Buffer1
BUF1FULL
Buffer2
BUF2FULL
ACK1
Full
Full
leads to assertion of the HIGHWAY BANDWIDTH ER-
ROR condition. One or more data samples are lost. Cap-
ture resumes at the correct memory address as soon as
the internal buffer is written to memory. The HBE error
condition is sticky. It remains asserted until it is cleared
by writing a ‘1’ to HIGHWAY BANDWIDTH ERROR
ACK. Refer to
Note that VI hardware uses copies of the BASE and SIZE
registers once capture has started. Modifications of
BASE or SIZE, therefore, have no effect until the start of
the next use of the corresponding buffer.
Note also that the VI_BASE1 and VI_BASE2 addresses
must be 64-byte aligned (the six LSBs are always ‘0’).
6.6
In this mode, VI receives 8-bit message data over the
VI_DATA[7:0] pins. The message data is written in
packed form (four 8-bit message bytes per 32-bit word)
to SDRAM. Message data capture starts on receipt of a
START event on VI_DATA[8]. Message data is received
until EndOfMessage (EOM) is received on VI_DATA[9]
or the receive buffer is full. Note that the VI_SIZE MMIO
register determines the buffer size, and hence maximum
message length. It should not be changed without a VI
(soft) reset.
Figure 6-17
transfer. The first byte (D0) is sampled on the rising edge
of the VI_CLK clock after a valid START was sampled on
the preceding rising clock edge. The last byte (D7) is
PRELIMINARY SPECIFICATION
MESSAGE-PASSING MODE
illustrates an example of an 8-byte message
Section 6.7, “Highway Latency and HBE.”
* OVERRUN is a sticky flag. It is set but does not af-
fect operation. It can only be cleared by software, by
writing a ‘1’ to ACK_OVR.
(See text in
raise OVERRUN*
BUF1FULL
BUF2FULL
Section
6.5)
Video In
6-11