PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 259

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
17.4
17.4.1
Write the SSI_CTL to reset and enable the transmitter.
Both the transmitter and receiver must be reset simulta-
neously. This will set all registers and internal logic to be
same as after a power-up reset. The recommended pro-
cedure is to set up all transmitter-related control bits be-
fore performing a TXE assert. In particular, fields TCP,
RSD, IO1, IO2, FMS, FSP, MOD and TMS should NOT
be changed after enabling the transmitter until after the
next transmitter reset.
The TxCLK is taken from the SSI_IO1 pin or from the re-
ceive clock, dependent on SSI_CTL.IO1. The direction of
shift in the TxSR and the clock edge on which to shift
must also be configured in SSI_CTL. If the DSPCPU
does not poll the SSI status registers, it should enable
the transmitter interrupt and set the ILS field by writing to
the SSI_CTL to allow interrupt driven servicing of the
SSI. Note that both transmit and receive use the same
ILS field. Set the framing controls, slot size, and mode re-
quired according to the external communication circuit’s
requirements by writing the SSI_CTL. Finally, set the in-
terrupt level to respond to empty levels in the TxFIFO.
Note that the Rx and Tx machines share the framing and
clock divide controls. They cannot be set to different val-
ues for Rx and Tx.
If the RxCLK used to derive the TxCLK needs a divide by
two, this is done by setting SSI_CSR.CD2.
17.4.2
The transmit state machine will wait for transmit data to
be written to the SSI_TxDR register. (see also
Figure
Figure 17-6. The transmit buffer operation
Hiway
From
17-6) As soon as SSI_TxDR is written, it’s value
SSI TRANSMIT OPERATION
Setup SSI_CTL
Operation Details
SSI_TxDR
29
28
27
...
...
...
30-depth of 16-bit buffer
...
...
7
will be propagated through two entries of the TxFIFO
(TxFIFO is 16-bit and SSI_TxDR is 32-bit) and trans-
ferred to TxSR, synchronized to TxFSX. The order of
transferring the two 16-bit parts in the 32-bit SSI_TxDR
can be configured by the endian bit SSI_CTL.EMS. Data
will begin shifting out of TxSR, one bit for each active
edge of the TxCLK, from either bit 15 (MSB first SSI_CTL
setting) or from bit 0 (LSB first) until TxSR is empty. For
endian control and shift direction see also subsection
17.8. When the shift register is empty, the transmit state
machine will load the value from the next available
TxFIFO location and begin shifting out that data. The
transmission continues until the transmit state machine
is disabled or reset.
If the last available TxFIFO has not been updated at the
appropriate time to reload TxSR, the last transmitted
frame is retransmitted and a transmit underrun error is in-
dicated in the transmitter status SSI_CSR.TUE
17.4.3
The refill status of the SSI_TxDR register is stored in
SSI_CSR. As the transmit state machine loads a TxFIFO
register to the TxSR, it sets the associated status bits.
The SSI will generate an internal interrupt when the num-
ber of empty words in the TxFIFO rises above the level
set by SSI_CSR.ILS. If the transmit state machine at-
tempts to read a TxFIFO while the last available TxFIFO
has not been updated, it will set the transmit underrun bit.
This can cause a protocol error in the transmission.
The number of available word buffers (SSI_CSR.WAW)
and transmitter data register empty (SSI_CSR.TDE) in-
formation is updated automatically by the SSI block.
PRELIMINARY SPECIFICATION
6
5
Interrupt and Status
4
3
Synchronous Serial Interface
wr_ptr
2
rd_ptr
1
0
SSI_TxDATA
16-bit
17-5