MT28C6428P20FM-80 TET Micron Technology Inc, MT28C6428P20FM-80 TET Datasheet - Page 29

• Manufacturer Part Number: MT28C6428P20FM-80 TET
• Manufacturer: Micron Technology Inc

Specifications of MT28C6428P20FM-80 TET

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

is complete, any possible error during the ERASE can-
not be detected via the status register because of the
previous locking command error.
a program operation error nested within an ERASE
SUSPEND.
CHIP PROTECTION REGISTER
fullfill the security considerations in the system (pre-
venting device substitution).
segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit number. The
other segment is left blank for customers to program as
desired. (See Figure 12).
READING THE CHIP PROTECTION REGISTER
identification mode. To enter this mode, load the 90h
command the bank containing address 00h. Once in
this mode, READ cycles from addresses shown in Table
10 retrieve the specified information. To return to the
read array mode, write the READ ARRAY command
(FFh). The READ ARRAY command, FFh, must be is-
sued to the bank containing address 00h prior to issu-
ing other commands.
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02
A similar situation happens if an error occurs during
A 128-bit chip protection register can be used to
The 128-bit security area is divided into two 64-bit
The chip protection register is read in the device
NOTE: 1. Other locations within the configuration address space are reserved by
ITEM
Manufacturer Code (x16)
Device Code
·
·
Block Lock Configuration
·
·
·
Chip Protection Register Lock
Chip Protection Register 1
Chip Protection Register 2
Top boot configuration
Bottom boot configuration
Block is unlocked
Block is locked
Block is locked down
2. “XX” specifies the block address of lock configuration.
Micron for future use.
Chip Configuration Addressing
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
Table 10
29
512K x 16 SRAM COMBO MEMORY
ADDRESS
00000h
00001h
XX002h
80h
81h–84h
85h–88h
PAGE READ MODE
same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0–A2 allows random ac-
cess of other words in the page.
four or eight words as required; but if no specification is
made, the normal size is four words.
ASYNCHRONOUS READ CYCLE
when switching between pages, the access time is given
by
on the data bus and the processor can read the data.
t
The initial portion of the page mode cycle is the
The page size can be customized at the factory to
When accessing addresses in a random order or
When F_CE# and F_OE# are LOW, the data is placed
AA.
Protection Register Memory Map
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
88h
85h
84h
81h
80h
Factory-Programmed
PR Lock
DATA
002Ch
44B6h
44B7h
Lock
DQ0 = 0
DQ0 = 1
DQ1 = 1
PR Lock
Factory Data
User Data
User-Programmed
1
Figure 12
4 Words
4 Words
0
©2002, Micron Technology, Inc.