MT28C6428P20FM-80 TET Micron Technology Inc, MT28C6428P20FM-80 TET Datasheet
MT28C6428P20FM-80 TET
Specifications of MT28C6428P20FM-80 TET
Related parts for MT28C6428P20FM-80 TET
MT28C6428P20FM-80 TET Summary of contents
Page 1
... S_LB# S_OE# DQ9 DQ8 DQ0 S_UB# A18 A17 NC NC F_V A4 A0 F_CE# F_V F_OE Top View (Ball Down) = 1.70V–1.90V CC = 1.80V–2.20V + +85 C) Part Number Example: MT28C6428P20FM-80 BET DQ7 DQ5 F_V CC DQ3 DQ1 S_CE1 MARKING -80 - None ET FM ©2002, Micron Technology, Inc. ...
Page 2
... CC bility when required. The data retention S_V Cross Reference for Abbreviated Device Marks PART NUMBER MT28C6428P20FM-80 BET MT28C6428P20FM-80 TET MT28C6428P18FM-85 BET MT28C6428P18FM-85 TET 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY fied as low as 1 ...
Page 3
... SRAM (512K x 16) Read Mode Operation P = Asynchronous/Page Read PART NUMBER MT28C6428P20FM-80 BET MT28C6428P20FM-80 TET MT28C6428P18FM-85 BET MT28C6428P18FM-85 TET NOTE: 1. For part number combinations not listed in this table, please contact your Micron representative. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – ...
Page 4
... CSM F_WE# F_OE# WSM I/O Logic Address Input A0–A21 Buffer Address Latch 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BLOCK DIAGRAM F_V F_V CC PP Bank a ...
Page 5
... E10, C9, C10, Output C8, B10, F8, F7, E8, E6, D7, C7, B9 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0– ...
Page 6
... H2, H10, H11, H12 C6, D5, D6, – E7 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Flash Program/Erase Power Supply: [0.9V–2.2V or 11.4V–12.6V]. Operates as input at logic levels to control complete device protection. ...
Page 7
... Data output on upper byte only; lower byte High-Z. 9. Data input on lower byte only. 10. Data input on upper byte only. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ...
Page 8
... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Figure 2 Bottom Boot Block Device Bank b = 48Mb Block Block Size ...
Page 9
... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Figure 3 Top Boot Block Device Bank b = 48Mb Block Block Size ...
Page 10
... I/O pins DQ0–DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0–DQ7 (see Table 8). 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ...
Page 11
... WA: Word address of memory location to be written, or read WD: Data to be written at the location WA X: “Don’t Care” 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 3 ...
Page 12
... C0h Program Device First Protection Register Lock Device First Protection Register 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table 5 Command Descriptions DESCRIPTION Prepares for an accelerated program operation. ...
Page 13
... Invalid/Reserved D1h Check Block Second Erase Confirm 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table 5 DESCRIPTION If the previous command was an ERASE SETUP command, then the CSM closes the address and data latches, and it begins erasing the block indicated on the address pins ...
Page 14
... DQ0–DQ7 to the bank containing address 00h and the identification code address on the address 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY lines ...
Page 15
... Command State Machine Transition Table Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table (continued on next page Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 16
... Command State Machine Transition Table (continued Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table (continued on next page Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 17
... Command State Machine Transition Table (continued Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table (continued on next page Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 18
... Command State Machine Transition Table (continued MODE Read (array, status registers, device identification register, or query) Standby Output Disable Reset Write 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table ...
Page 19
... For in-factory programming, the APA, along with an optimized set of programming parameters, minimizes chip programming time when 11.4V ≤ F_V 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY For in-system programming, when 0.9V ≤ ...
Page 20
... Locked Block; Operation Aborted Operation to Locked Blocks SR0 RESERVED FOR FUTURE ENHANCEMENT 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY CHECK BLOCK ERASE and the second one to start the execution of the command ...
Page 21
... SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH ...
Page 22
... Command NO Finished Reading ? YES Issue PROGRAM RESUME Command PROGRAM Resumed 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND COMMENTS WRITE READ Standby Standby ...
Page 23
... Word Address Issue 32 sequences of Word Address and Word Data SR7 = 0? YES PROGRAM Complete 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND WRITE ...
Page 24
... SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH ...
Page 25
... ERASE Continued NOTE: 1. See Word Programming Flowchart for complete programming procedure. 2. See BLOCK ERASE Flowchart for complete erasure procedure. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ...
Page 26
... Block Address NO SR7 = 1? YES NO SR5 = 0? YES BLOCK ERASE Complete 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND COMMENTS WRITE WRITE READ Standby Error Micron Technology, Inc ...
Page 27
... Table 9 defines all of the possible locking states. NOTE: All blocks are software-locked upon comple- tion of the power-up sequence. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ...
Page 28
... It can only be cleared by reset or power- down, not by software. Table 9 shows the block locking state transition scheme. The READ ARRAY command, 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ...
Page 29
... NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. “XX” specifies the block address of lock configuration. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ...
Page 30
... PP PPLK operation results in an error, prompting the corre- sponding status register bit (SR3 set. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY A factory option provides in-system programming ...
Page 31
... AC test inputs are driven Q/2. Input rise and fall times (10% to 90%) < 5ns Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” ...
Page 32
... Any read operation performed while in suspend mode will add a current draw Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY 1 F_V ...
Page 33
... Any read operation performed while in suspend mode will add a current draw Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY 1 (continued) ...
Page 34
... F_RP# HIGH to output delay CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change READ cycle time RST# deep power-down 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY SYMBOL ...
Page 35
... Program suspend latency Erase suspend latency Chip programming time 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY -80 – ...
Page 36
... NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY VALID ADDRESS ...
Page 37
... SYMBOL MIN MAX MIN ACE 80 t AOE 25 t RWH 200 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY VALID ADDRESS ACE t RWH -85 = 1.70V–1.90V MAX UNITS ...
Page 38
... MIN MAX MIN ACE 80 t APA 30 t AOE 25 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY VALID ADDRESS VALID VALID ADDRESS ADDRESS ACE t AOE VALID ...
Page 39
... CC CC SYMBOL MIN MAX MIN t RWH 200 t RP 100 100 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY RESET OPERATION t RP -85 = 1.70V–1.90V MAX UNITS 250 ns ...
Page 40
... Top boot block device ……96KB blocks of 5F00, 0001 Bottom boot block device ……96KB blocks of 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ...
Page 41
... SRAM density, 8Mb (512K x 16) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table 12 CFI (continued) ...
Page 42
... S_CE1# S_CE2 S_WE# S_OE# S_UB# S_LB# 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY S_OE addresses A0–A3. S_UB# and S_LB# control the data width as described above. ...
Page 43
... Write to High-Z output Data to write time overlap Data hold from write time End write to Low-Z output 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY to 0.9V S_V ...
Page 44
... MIN MAX MIN LB Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY READ CYCLE 1 ; S_CE2, S_WE PREVIOUS DATA VALID READ CYCLE 2 (S_WE LZ( OLZ t LB LBLZ, t UBLZ t LBHZ, t UBHZ ...
Page 45
... MAX MIN LBW UBW Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY WRITE CYCLE (S_WE# CONTROL LBW, t UBW High-Z t WHZ -85 = 1.70V–1.90V MAX UNITS SYMBOL t 85 ...
Page 46
... MIN MAX MIN LBW UBW Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY WRITE CYCLE 2 (S_CE1# CONTROL LBW, t UBW WHZ -85 = 1.70V–1.90V MAX UNITS SYMBOL t 85 ...
Page 47
... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH ...
Page 48
... Updated the chip protection mode register information • Updated the block locking information Initial published release, ADVANCE, Rev. 1 ............................................................................................................... 1/02 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Micron Technology, Inc ...