MT28C6428P20FM-80 TET Micron Technology Inc, MT28C6428P20FM-80 TET Datasheet - Page 14

• Manufacturer Part Number: MT28C6428P20FM-80 TET
• Manufacturer: Micron Technology Inc

Specifications of MT28C6428P20FM-80 TET

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

CLEAR STATUS REGISTER
lock status bit (SR1), the F_V
program status bit (SR4), and the erase status bit (SR5)
of the status register. The CLEAR STATUS REGISTER
command (50h) allows the external microprocessor to
clear these status bits and synchronize to the internal
operations. When the status bits are cleared, the de-
vice returns to the read array mode.
READ OPERATIONS
ARRAY, READ PROTECTION CONFIGURATION REG-
ISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
FFh on DQ0–DQ7. Control signals F_CE# and F_OE#
must be at a logic LOW level (V
must be at a logic HIGH level (V
array. Data is available on DQ0–DQ15. Any valid ad-
dress within any of the blocks selects that address and
allows data to be read from that address. Upon initial
power-up or device reset, the device defaults to the
read array mode.
READ CHIP PROTECTION IDENTIFICATION DATA
of information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip iden-
tification data is read by entering the command code
90h on DQ0–DQ7 to the bank containing address 00h
and the identification code address on the address
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02
The internal circuitry can set, but not clear, the block
The following READ operations are available: READ
The array is read by entering the command code
The chip identification mode outputs three types
IL
PP
), and F_WE# and F_RP#
IH
) to read data from the
status bit (SR3), the
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
14
512K x 16 SRAM COMBO MEMORY
lines. Control signals F_CE# and F_OE# must be at a
logic LOW level (V
a logic HIGH level (V
configuration register. Data is available on DQ0–DQ15.
After data is read from protection configuration regis-
ter, the READ ARRAY command, FFh, must be issued to
the bank containing address 00h prior to issuing other
commands. See Table 10 for further details.
READ QUERY
face (CFI) data when the device is read (see Table 12).
Two bus cycles are required for this operation. It is
possible to access the query by writing the read query
command code 98h on DQ0–DQ7 to the bank contain-
ing address 0h. Control signals F_CE# and F_OE# must
be at a logic LOW level (V
must be at a logic HIGH level (V
query. The CFI data structure contains information
such as block size, density, command set, and electri-
cal specifications. To return to read array mode, write
the read array command code FFh on DQ0–DQ7.
READ STATUS REGISTER
code 70h on DQ0–DQ7. Two bus cycles are required for
this operation: one to enter the command code and a
second to read the status register. In a READ cycle, the
address is latched and register data is updated on the
falling edge of F_OE# or F_CE#, whichever occurs last.
Register data is updated and latched on the falling
edge of F_OE# or F_CE#, whichever occurs last.
The read query mode outputs common flash inter-
The status register is read by entering the command
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
), and F_WE# and F_RP# must be at
IH
) to read data from the protection
IL
), and F_WE# and F_RP#
IH
) to read data from the
©2002, Micron Technology, Inc.